Joseph T Demarco

US Patent:

20120198264, Aug 2, 2012

Filed:

Oct 31, 2011

Appl. No.:

13/285131

Inventors:

Joseph T. DeMarco - Tucson AZ, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

G06F 1/12

US Classification:

713401

Abstract:

Primary serial interface logic is synchronized by cycling through a plurality of delays upon power up of the serial interface until a synchronization bit pattern is located. A minimum delay and a maximum delay are determined for the primary serial interface logic, and a delay is set to a midpoint between the minimum delay and the maximum delay. Secondary serial interface logic is synchronized by cycling through a plurality of delays until the output of the secondary serial interface logic equals the output of the primary serial interface logic. A minimum delay and a maximum delay are determined for the secondary serial interface logic, and a delay is set to a midpoint between the minimum delay and the maximum delay.