Julian Peter Partridge

US Patent:

7026708, Apr 11, 2006

Filed:

Jul 11, 2003

Appl. No.:

10/631886

Inventors:

James W. Cady - Austin TX, US
Julian Partridge - Austin TX, US
James Wilder - Austin TX, US
David L. Roper - Austin TX, US
Jeff Buchle - Austin TX, US

Assignee:

Staktek Group L.P. - Austin TX

International Classification:

H01L 23/488
H05K 1/14

US Classification:

257686, 257737, 257738, 257777, 257778, 361749, 361803, 438108, 438109, 438125, 438613, 29830, 29840

Abstract:

The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.

US Patent:

7033861, Apr 25, 2006

Filed:

May 18, 2005

Appl. No.:

11/131812

Inventors:

Julian Partridge - Austin TX, US
David Roper - Austin TX, US

Assignee:

Staktek Group L.P. - Austin TX

International Classification:

H01L 21/44

US Classification:

438109

Abstract:

A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

US Patent:

7094632, Aug 22, 2006

Filed:

Jun 22, 2004

Appl. No.:

10/873847

Inventors:

James W. Cady - Austin TX, US
Julian Partridge - Austin TX, US
James Wilder - Austin TX, US
David L. Roper - Austin TX, US
Jeff Buchle - Austin TX, US

Assignee:

Staktek Group L.P. - Austin TX

International Classification:

H01L 21/44
H01L 21/48
H01L 21/50

US Classification:

438109, 438106, 438108, 257686

Abstract:

The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

US Patent:

7180167, Feb 20, 2007

Filed:

Dec 14, 2004

Appl. No.:

11/011469

Inventors:

Julian Partridge - Austin TX, US
James W. Cady - Austin TX, US
James Wilder - Austin TX, US
David L. Roper - Austin TX, US

Assignee:

Staktek Group L. P. - Austin TX

International Classification:

H01L 23/02

US Classification:

257686, 257777, 257723, 438109, 361749, 361789, 361803

Abstract:

The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

US Patent:

7304382, Dec 4, 2007

Filed:

May 18, 2006

Appl. No.:

11/436957

Inventors:

Ron Orris - Austin TX, US
Leland Szewerenko - Austin TX, US
Tim Roy - Driftwood TX, US
Julian Partridge - Austin TX, US
David L. Roper - Austin TX, US

Assignee:

Staktek Group L.P. - Austin TX

International Classification:

H01L 23/34

US Classification:

257723, 257777

Abstract:

The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

US Patent:

7323364, Jan 29, 2008

Filed:

Apr 25, 2006

Appl. No.:

11/411185

Inventors:

Julian Partridge - Austin TX, US
David Roper - Austin TX, US

Assignee:

Staktek Group L.P. - Austin TX

International Classification:

H01L 21/44

US Classification:

438109, 257E23034

Abstract:

A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

US Patent:

7371609, May 13, 2008

Filed:

Apr 30, 2004

Appl. No.:

10/836855

Inventors:

Julian Partridge - Austin TX, US

Assignee:

Staktek Group L.P. - Austin TX

International Classification:

H01L 21/00

US Classification:

438109, 257686, 361749

Abstract:

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.

US Patent:

7375418, May 20, 2008

Filed:

Jun 14, 2006

Appl. No.:

11/452532

Inventors:

Julian Partridge - Austin TX, US

Assignee:

Entorian Technologies, LP - Austin TX

International Classification:

H01L 23/02

US Classification:

257685, 257666, 257692, 257696, 257E25021, 257E25027, 257E25006, 257E25013, 257E25018, 257E23085

Abstract:

The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the constituent ICs are implemented in interposers or carrier structures oriented along the leaded sides of the stack and which extend beyond the perimeter of the feet of the leads of the constituent ICs or beyond the connective pads of the interposer. This leaves open to air flow, most of the transit section of the lower lead for cooling, but provides a less complex board structure for implementation of intra-stack connections.