Kenneth C Bell

US Patent:

7071752, Jul 4, 2006

Filed:

Jan 29, 2004

Appl. No.:

10/768365

Inventors:

Venkateswar R. Kowkutla - Plano TX, US
Shifeng Zhao - Dallas TX, US
Luis E. Ossa - Plano TX, US
Kenneth M. Bell - Windom TX, US
Anker Josefsen - Gentofte, DK
Lars Risbo - Copenhagen, DK

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/04

US Classification:

327291, 327299

Abstract:

A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

US Patent:

20020060605, May 23, 2002

Filed:

Aug 31, 2001

Appl. No.:

09/945027

Inventors:

Venkateswar Kowkutla - Plano TX, US
Shifeng Zhao - Dallas TX, US
Luis Ossa - Plano TX, US
Kenneth Bell - Windom TX, US
Anker Josefsen - Gentofte, DK
Lars Risbo - Kobenhavn, DK
Michael Tsecouras - Carrollton TX, US

International Classification:

H03F003/38

US Classification:

330/010000

Abstract:

A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

US Patent:

49390996, Jul 3, 1990

Filed:

Sep 21, 1989

Appl. No.:

7/411210

Inventors:

Michael R. Seacrist - Grapevine TX
Joe R. Trogolo - Plano TX
Kenneth M. Bell - Windom TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2980

US Classification:

437 31

Abstract:

A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction isolation is completed by the doping and diffusion of shallow junction isolation regions (46, 122) at the same time that deep collector regions (48) are formed. A JFET source region (74) and a drain region (76) are formed simultaneously with a VPNP emitter region (70). A JFET gate contact region (88) is formed simultaenously with a VPNP base contact region (84), a VPNP buried region contact (86) and optionally with the doping of a capacitor electrode (124).