Kenneth L Bell

Address:

12245 Chapel Vw Dr, Dallas, TX 75234

VIN:

2T1KR30E37C637086

Make:

TOYOTA

Model:

MATRIX

Year:

2007

US Patent:

7071752, Jul 4, 2006

Filed:

Jan 29, 2004

Appl. No.:

10/768365

Inventors:

Venkateswar R. Kowkutla - Plano TX, US
Shifeng Zhao - Dallas TX, US
Luis E. Ossa - Plano TX, US
Kenneth M. Bell - Windom TX, US
Anker Josefsen - Gentofte, DK
Lars Risbo - Copenhagen, DK

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/04

US Classification:

327291, 327299

Abstract:

A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

US Patent:

20020060605, May 23, 2002

Filed:

Aug 31, 2001

Appl. No.:

09/945027

Inventors:

Venkateswar Kowkutla - Plano TX, US
Shifeng Zhao - Dallas TX, US
Luis Ossa - Plano TX, US
Kenneth Bell - Windom TX, US
Anker Josefsen - Gentofte, DK
Lars Risbo - Kobenhavn, DK
Michael Tsecouras - Carrollton TX, US

International Classification:

H03F003/38

US Classification:

330/010000

Abstract:

A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

US Patent:

49390996, Jul 3, 1990

Filed:

Sep 21, 1989

Appl. No.:

7/411210

Inventors:

Michael R. Seacrist - Grapevine TX
Joe R. Trogolo - Plano TX
Kenneth M. Bell - Windom TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2980

US Classification:

437 31

Abstract:

A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction isolation is completed by the doping and diffusion of shallow junction isolation regions (46, 122) at the same time that deep collector regions (48) are formed. A JFET source region (74) and a drain region (76) are formed simultaneously with a VPNP emitter region (70). A JFET gate contact region (88) is formed simultaenously with a VPNP base contact region (84), a VPNP buried region contact (86) and optionally with the doping of a capacitor electrode (124).

US Patent:

58924710, Apr 6, 1999

Filed:

May 14, 1997

Appl. No.:

8/856497

Inventors:

Shivaling Mahant-Shetti - Garland TX
Kenneth M. Bell - Windom TX
Sami Kiriaki - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 166

US Classification:

341135

Abstract:

A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21. sub. 0 -21. sub. N-1 and 25. sub. 0 -25. sub. N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.

US Patent:

20150222890, Aug 6, 2015

Filed:

Apr 15, 2015

Appl. No.:

14/687109

Inventors:

- Taoyuan Hsien, TW
Harold BELLIS - Garland TX, US
Adam KUNZMAN - Allen TX, US
Kenneth BELL - Plano TX, US

International Classification:

H04N 13/04
H04N 13/00

Abstract:

A dual-channel three-dimension projector is provided. The dual-channel three-dimension projector comprises a video processor, an FPGA, a first driver, a second driver and a digital micromirror device (DMD). The video processor receives a first video data via a first input interface and a second video data via a second input interface to generate a left-eye signal and a right-eye signal. The FPGA receives the left-eye signal and the right-eye signal via two paths respectively, and generates a left-image signal and a right-image signal. The first driver receives the left-image signal to generate a left-image control signal. The second driver receives the right-image signal to generate a right-image control signal. The DMD electrically connected to the first driver and the second driver alternately projects a left-eye image and a right-eye image according to the left-image control signal and the right-image control signal.