Kenneth Luis Potter

US Patent:

6529983, Mar 4, 2003

Filed:

Nov 3, 1999

Appl. No.:

09/432464

Inventors:

John William Marshall - Cary NC
Kenneth H. Potter - Raleigh NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

710200

Abstract:

A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of processors: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. The system is a programmable processing engine comprising an array of processor complex elements, each having a microcontroller processor. The processor complexes are preferably arrayed as rows and columns. Broadly stated, the novel GVLM comprises a lock controller function associated with each column of processor complexes and lock instructions executed by the processors that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources.

US Patent:

6662252, Dec 9, 2003

Filed:

Dec 8, 2002

Appl. No.:

10/314748

Inventors:

John William Marshall - Cary NC
Kenneth H. Potter - Raleigh NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

710200

Abstract:

A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of threads of execution: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. Broadly stated, the novel GVLM comprises a lock controller function associated with each thread of execution, and lock instructions executed by the threads that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources. The plurality of threads of execution may each execute in a different processor. Alternatively, the plurality of threads of execution may each execute in a single processor.

US Patent:

6757298, Jun 29, 2004

Filed:

Oct 10, 2000

Appl. No.:

09/685218

Inventors:

Barry S. Burns - Apex NC
Christopher J. Lefelhocz - Raleigh NC
Kenneth H. Potter - Raleigh NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04J 324

US Classification:

370473, 37039553

Abstract:

Virtual Local Area Network (VLAN) trunking over Asychronous Transfer Mode (ATM) Permanent Virtual Circuits (PVC), defined as VTAP, allows for aggregation of multiple VLAN traffic into a single data pipe in a Wide Area Network (WAN) environment. The largest benefit for the user is that a single PVC can be utilized to aggregate all of their VLAN traffic between two sites. Packets to be transmitted between two switches are first encapsulated with a VTAP header that contains pertinent information as to allow the receiving switch to process and forward the packet at the switch. Certain information contained in the VTAP is also used to determine the virtual path identifier/virtual channel identifier (VPI/VCI) of the destination switch wherein the packet is segmented into ATM cells having VPI/VCI prefixed to it for forwarding via the ATM network.

US Patent:

6804815, Oct 12, 2004

Filed:

Sep 18, 2000

Appl. No.:

09/663775

Inventors:

Darren Kerr - Palo Alto CA
Jeffery B. Scott - Durham NC
John William Marshall - Cary NC
Kenneth H. Potter - Raleigh NC
Scott Nellenbach - Apex NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 946

US Classification:

718100, 718107, 718108, 712218

Abstract:

A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i. e. , for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.

US Patent:

6895481, May 17, 2005

Filed:

Jul 3, 2002

Appl. No.:

10/189660

Inventors:

John W. Mitten - Cary NC, US
William R. Lee - Apex NC, US
Kenneth H. Potter - Raleigh NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F012/00

US Classification:

711154, 709250, 370498

Abstract:

A method for decrementing a reference count in a multicast environment is provided that includes receiving an access request for a particle stored in a memory element. The memory unit is then accessed in response to the access request, the particle being read from the memory element. The particle includes a plurality of data segments, a selected one or more of which includes a first reference count associated with the particle. The particle is then presented to a target that generated the access request. The first reference count associated with the selected one or more data segments is then decremented in order to generate a second reference count. At least one of the plurality of data segments with the second reference count is then written to the memory element.

US Patent:

7124231, Oct 17, 2006

Filed:

Jun 14, 2002

Appl. No.:

10/172172

Inventors:

Trevor Garner - Apex NC, US
Kenneth H. Potter - Raleigh NC, US
Hong-Man Wu - Raleigh NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 13/36

US Classification:

710310, 710112, 710 22, 710311

Abstract:

The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially issued over the split transaction bus, control logic is used to assign each request an identifying (ID) number, e. g. up to a maximum number of outstanding requests. Similarly, each response received over the split transaction bus is assigned the same ID number as its corresponding request. Accordingly, a “response memory” comprises a unique memory block for every possible ID number, and the control logic directs a received response to its corresponding memory block. The responses are extracted from blocks of response memory in accordance with a predetermined set of ordering rules. For example, the responses may be accessed in the same order the corresponding non-posted requests were issued.

US Patent:

7174394, Feb 6, 2007

Filed:

Jun 14, 2002

Appl. No.:

10/171957

Inventors:

Trevor Garner - Apex NC, US
Kenneth H. Potter - Raleigh NC, US
Robert Leroy King - Raleigh NC, US
William R. Lee - Apex NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 3/00

US Classification:

710 5, 710 7, 710 52, 712225

Abstract:

The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple processors to form requests for the coprocessor. Each received segment indicates a location in the context memory, such as an indexed memory block, where the segment should be stored. Illustratively, the write manager parses the received segments to their appropriate blocks of the context memory, and detects when the last segment for a request has been received. The last segment may be identified according to a predetermined address bit, e. g. an upper order bit, that is set. When the write manager receives the last segment for a request, the write manager (1) finishes assembling the request in a block of the context memory, (2) enqueues an index associated with the memory block in an index FIFO, and (3) sets a valid bit associated with memory block.

US Patent:

7447872, Nov 4, 2008

Filed:

May 30, 2002

Appl. No.:

10/158768

Inventors:

Russell Schroter - Apex NC, US
John William Marshall - Cary NC, US
Kenneth H. Potter - Raleigh NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 15/00

US Classification:

712 10, 712 16

Abstract:

An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.