Kenneth H Potter

US Patent:

6505269, Jan 7, 2003

Filed:

May 16, 2000

Appl. No.:

09/571213

Inventors:

Kenneth H. Potter - Raleigh NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

711 202, 711206, 711210

Abstract:

A dynamic address mapping technique eliminates contention to memory resources of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The technique defines two logical-to-physical address mapping modes that may be simultaneously provided to the processors of the arrayed processing engine to thereby present a single contiguous address space for accessing individual memory locations, as well as memory strings, within the memory resources. These addressing modes include a bank select mode and a stream mode.

US Patent:

6529983, Mar 4, 2003

Filed:

Nov 3, 1999

Appl. No.:

09/432464

Inventors:

John William Marshall - Cary NC
Kenneth H. Potter - Raleigh NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

710200

Abstract:

A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of processors: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. The system is a programmable processing engine comprising an array of processor complex elements, each having a microcontroller processor. The processor complexes are preferably arrayed as rows and columns. Broadly stated, the novel GVLM comprises a lock controller function associated with each column of processor complexes and lock instructions executed by the processors that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources.

US Patent:

6662252, Dec 9, 2003

Filed:

Dec 8, 2002

Appl. No.:

10/314748

Inventors:

John William Marshall - Cary NC
Kenneth H. Potter - Raleigh NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

710200

Abstract:

A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of threads of execution: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. Broadly stated, the novel GVLM comprises a lock controller function associated with each thread of execution, and lock instructions executed by the threads that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources. The plurality of threads of execution may each execute in a different processor. Alternatively, the plurality of threads of execution may each execute in a single processor.

US Patent:

6708258, Mar 16, 2004

Filed:

Jun 14, 2001

Appl. No.:

09/881280

Inventors:

Kenneth H. Potter - Raleigh NC
Trevor Garner - Apex NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

711154, 711155, 710 52

Abstract:

A computer system stores packet data and reduces the number of Read-Modify-Write (RMW) operations. An attribute is configured to specify a mode of operation that instructs the processor to perform a RMW operation, or to pad the packet data to over-write a memory line. A buffer defines the memory lines. Each memory line has a discrete number of bytes. The processor addresses the buffer with a memory address register. The attribute is a new bit in the memory address register. The attribute is configured to specify a mode of operation that instructs the processor to pad the packet data to be equal to one or more complete, full memory lines so that the padded packet data are stored only in complete, full memory lines, rather than to do an expensive RMW operation. The attribute may be a new bit added to the memory address register. A set value of the bit may indicate that a RMW operation is to be performed, and a clear value may indicate that padding of the packet data is to be done for the data to match the length of a memory line.

US Patent:

6757298, Jun 29, 2004

Filed:

Oct 10, 2000

Appl. No.:

09/685218

Inventors:

Barry S. Burns - Apex NC
Christopher J. Lefelhocz - Raleigh NC
Kenneth H. Potter - Raleigh NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04J 324

US Classification:

370473, 37039553

Abstract:

Virtual Local Area Network (VLAN) trunking over Asychronous Transfer Mode (ATM) Permanent Virtual Circuits (PVC), defined as VTAP, allows for aggregation of multiple VLAN traffic into a single data pipe in a Wide Area Network (WAN) environment. The largest benefit for the user is that a single PVC can be utilized to aggregate all of their VLAN traffic between two sites. Packets to be transmitted between two switches are first encapsulated with a VTAP header that contains pertinent information as to allow the receiving switch to process and forward the packet at the switch. Certain information contained in the VTAP is also used to determine the virtual path identifier/virtual channel identifier (VPI/VCI) of the destination switch wherein the packet is segmented into ATM cells having VPI/VCI prefixed to it for forwarding via the ATM network.

US Patent:

6757768, Jun 29, 2004

Filed:

May 17, 2001

Appl. No.:

09/859707

Inventors:

Kenneth H. Potter - Raleigh NC
Trevor Garner - Apex NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

710112

Abstract:

An apparatus and technique off-loads responsibility for maintaining order among requests issued over a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. A logic circuit enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until all pending (read) requests complete. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The logic circuit maintains the order of the requests in an efficient manner that is transparent to the processor.

US Patent:

6804815, Oct 12, 2004

Filed:

Sep 18, 2000

Appl. No.:

09/663775

Inventors:

Darren Kerr - Palo Alto CA
Jeffery B. Scott - Durham NC
John William Marshall - Cary NC
Kenneth H. Potter - Raleigh NC
Scott Nellenbach - Apex NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 946

US Classification:

718100, 718107, 718108, 712218

Abstract:

A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i. e. , for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.

US Patent:

6832279, Dec 14, 2004

Filed:

May 17, 2001

Appl. No.:

09/859709

Inventors:

Kenneth H. Potter - Raleigh NC
Trevor Garner - Apex NC

Assignee:

Cisco Systems, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

710112, 710 52

Abstract:

An apparatus and technique off-loads responsibility for maintaining order among requests directed to a same address on a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. The present invention comprises an ordering circuit that enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until a previous (read) request directed to the same address completes. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The ordering circuit maintains ordering in an efficient manner that is transparent to the processor.