Kenneth M Potter

US Patent:

6838400, Jan 4, 2005

Filed:

Mar 23, 1998

Appl. No.:

09/046105

Inventors:

Robert Maynard Japp - Vestal NY, US
Pamela Lulkoski - Vestal NY, US
Jeffrey McKeveny - Endicott NY, US
Jan Obrzut - Vestal NY, US
Kenneth Lynn Potter - Kirkwood NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 1702
B32B 1704
B32B 2704

US Classification:

442175, 428901, 428417, 442 60, 442172, 442180, 442301

Abstract:

The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.

US Patent:

6976149, Dec 13, 2005

Filed:

Feb 22, 2001

Appl. No.:

09/790968

Inventors:

William P. Brandt - Groton MA, US
Kenneth H. Potter - Raleigh NC, US
Jonathan Rosen - Cary NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F012/00

US Classification:

711220, 711209

Abstract:

A mapping technique allows a forwarding engine of an intermediate node to efficiently compute a starting address within an internal packet memory (IPM) configured to hold a packet received at the node. The starting address is used by direct memory access logic to merge a trailer of the packet stored in the IPM with a modified packet header generated by the forwarding engine. However, the size of the IPM is preferably not a binary number that can be easily manipulated by the forwarding engine when computing the starting address of the packet within the IPM. Therefore, the technique automatically adjusts the starting address to map to a correct location if the address exceeds the size of the IPM, while obviating the need for the forwarding engine to consider a wrap-around condition when computing the starting address.

US Patent:

7070909, Jul 4, 2006

Filed:

Aug 30, 2004

Appl. No.:

10/928178

Inventors:

Robert M. Japp - Vestal NY, US
Pamela Lulkoski - Vestal NY, US
Jeffrey McKeveny - Endicott NY, US
Jan Obrzut - Vestal NY, US
Kenneth Lynn Potter - Kirkwood NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 3/00
H05K 1/03

US Classification:

430311, 430319, 156 60, 428901

Abstract:

The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.

US Patent:

20010041308, Nov 15, 2001

Filed:

Jul 17, 2001

Appl. No.:

09/906984

Inventors:

Ashwinkumar Bhatt - Endicott NY, US
John Camp - Owego NY, US
Mary Fletcher - Vestal NY, US
Kenneth Potter - Kirkwood NY, US
John Welsh - Binghamton NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F007/00

US Classification:

430/312000, 430/315000, 430/319000

Abstract:

A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

US Patent:

20060067225, Mar 30, 2006

Filed:

Sep 24, 2004

Appl. No.:

10/949916

Inventors:

Guy Fedorkow - Bedford MA, US
Kenneth Potter - Raleigh NC, US
Mark Gustlin - Campbell CA, US
Christopher Kappler - Waltham MA, US
Robert Olsen - Dublin CA, US

International Classification:

H04L 12/56

US Classification:

370235000, 370395400

Abstract:

Presently disclosed is an apparatus and method for returning control of bandwidth allocation and packet scheduling to the routing engine in a network communications device containing an ATM interface. Virtual circuit (VC) flow control is augmented by the addition of a second flow control feedback signal from each virtual path (VP). VP flow control is used to suspend scheduling of all VCs on a given VP when traffic has accumulated on enough VCs to keep the VP busy. A new packet segmenter is employed to segment traffic while preserving the first in, first out (FIFO) order in which packet traffic was received. Embodiments of the invention may be implemented using a two-level (per-VC and per-VP) scheduling hierarchy or may use as many levels of flow control feedback-derived scheduling as may be necessitated by multilevel scheduling hierarchies.

US Patent:

62742914, Aug 14, 2001

Filed:

Nov 18, 1998

Appl. No.:

9/195010

Inventors:

Ashwinkumar C. Bhatt - Endicott NY
John C. Camp - Owego NY
Mary Beth Fletcher - Vestal NY
Kenneth Lynn Potter - Kirkwood NY
John A. Welsh - Binghamton NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 700

US Classification:

430312

Abstract:

A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

US Patent:

55997473, Feb 4, 1997

Filed:

Jun 27, 1995

Appl. No.:

8/495248

Inventors:

Ashwinkumar C. Bhatt - Endicott NY
Thomas P. Duffy - Endicott NY
David E. Houser - Apalachin NY
Gerald W. Jones - Apalachin NY
Jeffrey McKeveny - Endicott NY
Kenneth L. Potter - Kirkwood NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2160

US Classification:

437209

Abstract:

A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc. , which may adversely impact subsequent processing steps.