Kenneth G Potter

US Patent:

6804815, Oct 12, 2004

Filed:

Sep 18, 2000

Appl. No.:

09/663775

Inventors:

Darren Kerr - Palo Alto CA
Jeffery B. Scott - Durham NC
John William Marshall - Cary NC
Kenneth H. Potter - Raleigh NC
Scott Nellenbach - Apex NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 946

US Classification:

718100, 718107, 718108, 712218

Abstract:

A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i. e. , for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.

US Patent:

7286532, Oct 23, 2007

Filed:

Feb 22, 2001

Appl. No.:

09/791063

Inventors:

Ramesh Sivakolundu - Saratoga CA, US
Kenneth H. Potter - Raleigh NC, US
Guy C. Fedorkow - Bedford MA, US
Gary S. Muntz - Lexington MA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370391, 370389, 370420

Abstract:

An aggregation router architecture comprises a plurality of line cards coupled to at least one performance routing engine (PRE) via an interconnect system. The line cards include input cards having input ports coupled to subscribers and at least one trunk card configured to aggregate packets received from the subscriber inputs over at least one output port. The PRE performs packet forwarding and routing operations, along with quality of service functions for the packets received from each input line card over the interconnect system. The interconnect system comprises a plurality of high-speed unidirectional (i. e. , point-to-point) links coupling the PRE to each line card. The point-to-point links couple the line cards to a novel logic circuit of the PRE that is configured to interface the line cards to a packet buffer and a forwarding engine of the PRE.

US Patent:

20050100017, May 12, 2005

Filed:

Nov 12, 2003

Appl. No.:

10/706704

Inventors:

John Williams - Pleasanton CA, US
John Fingerhut - Campbell CA, US
Kenneth Potter - Raleigh NC, US

Assignee:

CISCO TECHNOLOGY, INC., A CALIFORNIA CORPORATION - SAN JOSE CA

International Classification:

H04L012/56

US Classification:

370394000

Abstract:

Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets may be particularly useful. One implementation uses a locking request, acceptance, and release protocol. One implementation associates instructions with locking requests such that when a lock is acquired, the locking mechanism executes or causes to be executed the associated instructions as an acceptance request of the lock is implied by the association of instructions (or may be explicitly requested). In some applications, the ordering of the entire sequence of packets is not required to be preserved, but rather only among certain sub-sequences of the entire sequence of items, which can be accomplished by converting an initial root ordered lock (maintaining the sequence of the entire stream of items) to various other locks (each maintaining a sequence of different sub-streams of items).