Kenneth Alan Wagner

US Patent:

6389566, May 14, 2002

Filed:

Jun 2, 1998

Appl. No.:

09/088754

Inventors:

Kenneth D. Wagner - Sunnyvale CA
Srinivasan R. Iyengar - Fremont CA
Mehran Amerian - Campbell CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714726, 327202

Abstract:

An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.

US Patent:

61580333, Dec 5, 2000

Filed:

May 8, 1998

Appl. No.:

9/075350

Inventors:

Kenneth D. Wagner - Sunnyvale CA
Mehran Amerian - Campbell CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714726

Abstract:

An integrated circuit includes a first circuit module for generating a plurality of digital signals and a second circuit module for receiving the digital signals. A multiple input signature module receives the digital signals that are received by the second circuit module. The signature module generates and stores a signature value which is indicative of data values of the digital signals over a plurality of cycles. The signature module operates in response to control circuitry, which is responsive to a test signal, to cause the values indicative of the digital signals to be stored to the multiple input signature module, each time that valid signal values are received by the second circuit module. The multiple input signature module may be used for diagnostics by capturing data at a single, predetermined cycle. The module may be initialized to a predetermined value to ensure the signature value or, the single value captured, accurately reflects the data value of the digital signals.

US Patent:

61694185, Jan 2, 2001

Filed:

Jun 24, 1998

Appl. No.:

9/103757

Inventors:

Kenneth D. Wagner - Sunnyvale CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

H03K 19177
H01L 2500
G11C 506

US Classification:

326 41

Abstract:

An improved routing system and method allow routing of pluralities of signals to circuit blocks on integrated circuit chips using minimal die area. The improved routing system employs a plurality of tri-state buffers, a plurality of conductive lines, and a controller. The circuit block can be driven from remote locations via the tri-state buffers and conductive lines. The tri-state buffers are selectively enabled one at a time by the controller to prevent signal contention. The multiplexors encountered in conventional routing systems are not needed. The improved routing system and method are ideal for routing to and from large circuit blocks which have numerous terminals, such as embedded dynamic random access memory units, embedded static random access memory units, central processing units, arithmetic logic units, register files, and cores generally. The improved routing system and method also allow testing of large circuit blocks with test vectors supplied by built in self test units and or off-chip test equipment.

US Patent:

56967713, Dec 9, 1997

Filed:

May 17, 1996

Appl. No.:

8/649788

Inventors:

James Beausang - Mountain View CA
Kenneth Wagner - Sunnyvale CA
Robert Walker - Boulder CO

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

A computer implemented process and system for effectively determining a set of sequential cells with a integrated circuit design that can be scan replaced (e. g. for design for test applications) to offer significant testability while still maintaining specified optimization (e. g. , area and/or timing) constraints that are applicable to the design. The novel system selects sequential cells for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design. The novel system is composed of a subtractive method and an additive method. The subtractive method inputs a fully scan replaced netlist (e. g. , the sequential cells are scan replaced) that does not meet determined optimization constraints.

US Patent:

60676507, May 23, 2000

Filed:

Dec 5, 1997

Appl. No.:

8/985614

Inventors:

James Beausang - Mountain View CA
Kenneth Wagner - Sunnyvale CA
Robert Walker - Boulder CO

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G01R 3128

US Classification:

714726

Abstract:

A computer implemented process and system for effectively determining a set of sequential cells with a integrated circuit design that can be scan replaced (e. g. for design for test applications) to offer significant testability while still maintaining specified optimization (e. g. , area and/or timing) constraints that are applicable to the design. The novel system selects sequential cells for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design. The novel system is composed of a subtractive method and an additive method. The subtractive method inputs a fully scan replaced netlist (e. g. , the sequential cells are scan replaced) that does not meet determined optimization constraints.