Kenneth E Wright

US Patent:

6473772, Oct 29, 2002

Filed:

Dec 17, 1998

Appl. No.:

09/213913

Inventors:

Jason Raymond Baumgartner - Austin TX
Sriram Srinivasan Mandyam - Austin TX
Robert James Ramirez - New Braunfels TX
Brett Adam St. Onge - Austin TX
Kenneth Lee Wright - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1730

US Classification:

7071041, 707100, 703 17

Abstract:

A method and apparatus for dynamically driving events in a simulation of a data processing system are implemented. Events, or system states, are generated by drivers located at predetermined locations within the simulation model under test. These events, which are drawn from a predetermined class of events, termed âeffects,â are driven in response to other events observed by monitors disposed within the simulation model in accordance with a predetermined set of âcauses,â and a set of ârulesâ that map causes to effects. The driving of events is mediated by a library process that receives observed events from the monitors, in the form of data structures, stored them in a database, and passes the effects to be driven to the appropriate driver in accordance with the set of rules, also data structures stored in the database, when a cause corresponds to a observed event.

US Patent:

6629228, Sep 30, 2003

Filed:

Sep 21, 2000

Appl. No.:

09/666275

Inventors:

Steven Robert Farago - Austin TX
Kenneth Lee Wright - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711170, 711154

Abstract:

A method, system, and apparatus for managing data elements in a storage area is disclosed. A storage area, with a first and second end, is provided for storing data elements. The data elements are stored in a first stack, also having a first and second end. Space in the storage area for the first stack includes a first space proximate the first end of the first stack, and a second space proximate the second end of the first stack. The storing of one of the data elements in the first stack includes selecting between storing in the first space or the second space, responsive to the relative sizes of the two spaces. Data elements are also stored in the storage area in a second stack. Space available in the storage area for data elements of the second stack includes the above mentioned first and second spaces, that is, the space proximate the first end of the first stack, and the space proximate the second end of the first stack. Storing in the second stack also includes selecting between storing in the first or second space, responsive to the relative sizes of the two spaces.

US Patent:

6643662, Nov 4, 2003

Filed:

Sep 21, 2000

Appl. No.:

09/667751

Inventors:

Steven Robert Farago - Austin TX
Kenneth Lee Wright - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1730

US Classification:

707101, 711132

Abstract:

In a method, system, and apparatus for managing storage of data elements, a storage area having a first and second end is provided for storing the data elements. In the storage area, a first stack of data elements has first and second ends respectively facing the first and second ends of the storage area, and a second stack has data elements located proximate both ends of the first stack. That is, the second stack is split, with the first stack interposed between data elements of the second stack. Likewise, there may be a third and fourth stack, and so on, which are split into more than one part. The stacks increase in size toward both the first end of the storage area and the second end of the storage area, responsive to the storing of successive ones of the data elements in the respective stacks. Furthermore, the increasing in size of one of the split stacks may include increasing away from the first stack, or alternatively, increasing toward the first stack.

US Patent:

6785773, Aug 31, 2004

Filed:

Mar 29, 2001

Appl. No.:

09/821078

Inventors:

Steven Robert Farago - Austin TX
Lawrence Allyn McConville - Austin TX
Kenneth Lee Wright - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141, 711146, 711155, 714 37, 714 47, 714 51

Abstract:

A system and method for verifying cache coherency in a multi-node, NUMA system includes a transaction modification unit configured to receive event traces generated by a simulation tool. The modification unit modifies transactions that are propagated to another node in the NUMA system and thus result in two bus transactions, a home node transaction (HNT) and a foreign node transaction (FNT). More specifically, the modification unit merges a FNT and its corresponding HNT into a single merge transaction (MT) under a prescribed set of merging rules. The MT has properties of the both the FNT and the HNT. The FNT and HNT are deleted from the event trace and replaced by their corresponding MT to create a modified event trace that is suitable for coherency checking by a single system coherency checker.

US Patent:

6795878, Sep 21, 2004

Filed:

Dec 11, 2000

Appl. No.:

09/734115

Inventors:

Aaron Ches Brown - Austin TX
Steven Robert Farago - Austin TX
Robert James Ramirez - Chicago IL
Kenneth Lee Wright - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1337

US Classification:

710 43, 710 39, 710 40, 710125, 711151, 711158

Abstract:

A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified. Upon identifying the first and second reloads of the first and second cache lines, a determination may be made as to whether the first reload occurred after the second.

US Patent:

6904490, Jun 7, 2005

Filed:

Oct 10, 2002

Appl. No.:

10/268743

Inventors:

Ravi Kumar Arimilli - Austin TX, US
John Steven Dodson - Pflugerville TX, US
Sanjeev Ghai - Round Rock TX, US
Kenneth Lee Wright - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711 5, 711 4, 711114, 711161, 711162, 711200, 711203, 711209

Abstract:

A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the mapping engine maps Write memory requests addressed to the real address space currently associated with the reconfigured memory module to both the FROM and TO real address space. As will be appreciated, a memory module can be inserted, removed or replaced in physical memory without the operating system having to direct and control the reconfiguration of physical memory to accomplish the physical memory change.

US Patent:

6907494, Jun 14, 2005

Filed:

Oct 10, 2002

Appl. No.:

10/268728

Inventors:

Ravi Kumar Arimilli - Austin TX, US
John Steven Dodson - Pflugerville TX, US
Sanjeev Ghai - Round Rock TX, US
Kenneth Lee Wright - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711 5, 711 4, 711100, 711114, 711200, 711202, 711209, 711161, 711162

Abstract:

A processor contains a move engine and a memory controller contains a mapping engine that, together, transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores current and new real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the current and new real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory modules. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the mapping engine responds to Write memory requests addressed to either the current or new real address space. As will be appreciated, a memory module can be inserted, removed or replaced in physical memory without the operating system having to direct and control the reconfiguration of physical memory to accomplish the physical memory change.

US Patent:

6920521, Jul 19, 2005

Filed:

Oct 10, 2002

Appl. No.:

10/268741

Inventors:

Ravi Kumar Arimilli - Austin TX, US
John Steven Dodson - Pflugerville TX, US
Sanjeev Ghai - Round Rock TX, US
Kenneth Lee Wright - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711 5, 711 4, 711100, 711114, 711200, 711202, 711209

Abstract:

A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the operating system stalls. Write memory requests addressed to the real address space currently associated with the sourcing memory module indicated by either the FROM or TO real address space.