Kiet Q Tran

US Patent:

7298746, Nov 20, 2007

Filed:

Apr 22, 2002

Appl. No.:

10/127372

Inventors:

Erik De La Iglesia - Mountain View CA, US
Miguel Gomez - Fremont CA, US
Rahoul Puri - Los Altos CA, US
Chien C. Chou - San Jose CA, US
Kiet Tran - Saratoga CA, US

Assignee:

Extreme Networks - Santa Clara CA

International Classification:

H04L 12/56

US Classification:

370394

Abstract:

A packet reassembly system includes a buffer for storing information elements included in one or more incoming packets, a memory for storing validity indicators corresponding to the information elements, a first logic circuit capable of setting the validity indicators based on the information elements stored in the buffer, and a second logic circuit capable of determining the contiguity of the information elements stored in the buffer based on the settings of the validity indicators.