Kiet Chi Tran

US Patent:

6665753, Dec 16, 2003

Filed:

Aug 10, 2000

Appl. No.:

09/637317

Inventors:

Pat Allen Buckland - Austin TX
Michael Anthony Perez - Cedar Park TX
Kiet Anh Tran - Cedar Park TX
Adalberto Guillermo Yanes - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300

US Classification:

710 52, 710 36, 710 54, 710 65, 709 24

Abstract:

A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.

US Patent:

6665759, Dec 16, 2003

Filed:

Mar 1, 2001

Appl. No.:

09/798294

Inventors:

George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
David Lee Randall - Leander TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1214

US Classification:

710200, 710 22, 710 26, 710 27, 710 28, 710308, 710312, 710313, 710314, 710315, 711152, 711153

Abstract:

A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

US Patent:

6717594, Apr 6, 2004

Filed:

Sep 25, 2000

Appl. No.:

09/668549

Inventors:

Tam D. Bui - Austin TX
George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
Jayeshkumar M. Patel - Austin TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06T 1500

US Classification:

345763, 345501, 345522, 345965, 709221, 709222, 713 1, 713 2

Abstract:

A data processing system and method are disclosed for displaying a graphical depiction of the system configuration of the data processing system. Execution of a boot process of the data processing system is started. Prior to a completion of the boot process, a configuration of the data processing system is determined by the system itself. A graphical depiction of the configuration is then generated. The graphical depiction is then graphically displayed utilizing a display screen which is included in the data processing system. The graphical depiction illustrates each device included in the system as well as how the devices are interconnected. Thereafter, the execution of the boot process is completed. The steps of determining a configuration, generating a graphical depiction, and graphically displaying the graphical depiction are completed prior to completing the booting the data processing system, and thus prior to an operating system being executed by the data processing system.

US Patent:

6728864, Apr 27, 2004

Filed:

Jan 31, 2001

Appl. No.:

09/773192

Inventors:

Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1576

US Classification:

712200, 712 32, 712220

Abstract:

A method, system and program for architecturally identifying data processor implementations are provided. The invention comprises assigning a plurality of least significant bits in a processors identification register to a unique value. This value can be assigned to these bits permanently during manufacture and is used to identify the bit specification for a specific processor implementation. The present invention can be generalized to include any processor architecture that comprises a plurality of instruction subsets for different bit specifications.

US Patent:

6745269, Jun 1, 2004

Filed:

Jan 11, 2001

Appl. No.:

09/758736

Inventors:

Tam D. Bui - Austin TX
George John Dawkins - Austin TX
Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710104, 713 1, 713 2, 713100

Abstract:

A method and apparatus preserve the data structures established in the earliest stage of initial power load, rather than each system firmware component rediscovering the hardware components of the system. Thus, the data structure is available at later stages for other firmware components. In a logical partitioning machine, the open firmware partition manager can utilize the data structure to support the partitions open firmware device tree construction. The partition manager customizes the copies of these data structures residing in the partitions memory. For hardware devices in the system but not belonging to the partition, the device information is cleared and marked invalid. After the data structures are established and updated by the earliest firmware I/O configuration component, the addresses of these structures are provided to the open firmware component. The open firmware copies these data structures to its internally safe working area and uses the copies for its normal operation. When runtime abstraction service firmware component is instantiated, the addresses of the structures of open firmwares copies are provided by the open firmware component to runtime abstraction service.

US Patent:

6823375, Nov 23, 2004

Filed:

Mar 1, 2001

Appl. No.:

09/798163

Inventors:

Van Hoa Lee - Cedar Park TX
Kiet Anh Tran - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15177

US Classification:

709220, 709221, 709222, 370254, 710 8

Abstract:

A method, system, and product are described for configuring remote input/output (RIO) hubs within a data processing system. Each one of the RIO hubs is assigned to one of multiple slave processors which are included within the data processing system. Each one of the slave processors which has an assigned RIO hub then configures its assigned RIO hub. Each RIO hub has an associated data structure that is updated with current configuration information by the slave processor assigned to configure that RIO hub. When the slave processor has finished configuring its assigned RIO hub, the slave processor then sets a configuration flag to indicate the completion of the configuration of the RIO hub.

US Patent:

6842857, Jan 11, 2005

Filed:

Apr 12, 2001

Appl. No.:

09/833337

Inventors:

Van Hoa Lee - Cedar Park TX, US
Kiet Anh Tran - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900
G06F 15177
G06F 15167

US Classification:

713 2, 713 1, 713100, 709200, 709201, 709213, 709214, 709215, 709216

Abstract:

A method, apparatus and program for booting a non-uniform-memory-access (NUMA) machine are provided. The invention comprises configuring a plurality of standalone, symmetrical multiprocessing (SMP) systems to operate within a NUMA system. A master processor is selected within each SMP; the other processors in the SMP are designated as NUMA slave processors. A NUMA master processor is then chosen from the SMP master processors; the other SMP master processors are designated as NUMA slave processors. A unique NUMA ID is assigned to each SMP that will be part of the NUMA system. The SMPs are then booted in NUMA mode in one-pass with memory coherency established right at the beginning of the execution of the system firmware.

US Patent:

6957252, Oct 18, 2005

Filed:

Oct 12, 2000

Appl. No.:

09/687099

Inventors:

Tam D. Bui - Austin TX, US
Chetan Mehta - Austin TX, US
Keng-Hiup Ng - Kuala Lumpur, MY
Jayeshkumar M. Patel - Ausitn TX, US
Amir Simon - Austin TX, US
Kiet Anh Tran - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F015/16

US Classification:

709220, 709221

Abstract:

A method, system, and apparatus for synchronizing device, node, and drawer addresses between two networks within a data processing system is provided. In one embodiment, a service processor assigns a plurality of SPCN addresses to each of a plurality of devices in the data processing system. System firmware then determines the RIO addresses corresponding to the plurality of devices. If one of the SPCN addresses is not the same as the RIO address for the corresponding device, node, or drawer, then the service processor reassigns a new SPCN address to the corresponding device, node, or drawer such that the new SPCN address is identical to the RIO address for a corresponding device, node, or drawer.