Krishna O Rajan

US Patent:

20030149926, Aug 7, 2003

Filed:

Feb 7, 2002

Appl. No.:

10/072342

Inventors:

Krishna Rajan - Newark CA, US

International Classification:

G01R031/28

US Classification:

714/726000

Abstract:

Disclosed are novel methods and apparatus for efficiently providing a single scan chain design for hierarchically BISTed designs. In an embodiment, a method of providing a single scan chain of a chip is disclosed. The method includes: selecting a TOP chain of the chip, the chip being divided into a plurality of embedded logic test (ELT) blocks; bypassing periphery flops of the plurality of ELT blocks; selecting a single scan chain of all ELT blocks of the chip; and inserting the single scan chain of all ELT blocks of the chip into the TOP chain of the chip.

US Patent:

20030188243, Oct 2, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/113365

Inventors:

Krishna Rajan - Newark CA, US

International Classification:

G01R031/28

US Classification:

714/731000

Abstract:

A TAP-controlled scan architecture is modified to include an additional pin to receive a double capture mode (DCM) signal that may be used to override a functional mode signal provided by a TAP controller to enable an externally generated functional clock to provide double capture clock pulses to an internal scan chain during testing without transitioning the TAP controller between states.