Kwong M Wong

US Patent:

6383929, May 7, 2002

Filed:

Jan 11, 2001

Appl. No.:

09/759015

Inventors:

Steven H. Boettcher - Fishkill NY
Herbert L. Ho - Cornwall NY
Mark Hoinkis - Fishkill NY
Hyun Koo Lee - LaGrangeville NY
Yun-Yu Wang - Poughquag NY
Kwong Hon Wong - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk
Infineon Technologies North America Corp. - San Jose CA

International Classification:

H01L 2144

US Classification:

438687, 438643, 438644, 438653, 438654

Abstract:

In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

US Patent:

6388327, May 14, 2002

Filed:

Jan 9, 2001

Appl. No.:

09/756938

Inventors:

Kenneth J. Giewont - Hopewell Junction NY
Stephen Bruce Brodsky - Wappingers Falls NY
Cyril Cabral, Jr. - Ossining NY
Anthony G. Domenicucci - New Paltz NY
Craig Mitchell Ransom - Hopewell Junction NY
Yun-Yu Wang - Poughquag NY
Horatio S. Wildman - Wappingers Falls NY
Kwong Hon Wong - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257754, 257751, 257758

Abstract:

A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.

US Patent:

6399490, Jun 4, 2002

Filed:

Jun 29, 2000

Appl. No.:

09/607131

Inventors:

Rajarao Jammy - Wappingers Falls NY
Cheryl G. Faltermeier - Lagrange NY
Uwe Schroeder - Fishkill NY
Kwong Hon Wong - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438680, 438668, 438685, 42725536, 427255391, 427585

Abstract:

Process for forming highly conformal titanium nitride on a silicon substrate. A gaseous reaction mixture of titanium tetrachloride and ammonia is passed over the semiconductor substrate surface maintained at a temperature of about 350Â C. to about 800Â C. The ratio of titanium tetrachloride to ammonia is about 5:1 to 20:1. The high degree of conformality achieved by the process of the invention allows TiN layers to be deposited on structures with high aspect ratios and on complicated, three-dimensional structures without forming a large seam or void.

US Patent:

6436760, Aug 20, 2002

Filed:

Apr 19, 2001

Appl. No.:

09/838418

Inventors:

Kwong H. Wong - Wappingers Falls NY
Ashima B. Chakravarti - Hopewell Junction NY
Satya N. Chakravarti - Hopewell Junction NY
Subramanian S. Iyer - Mount Kisco NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 218242

US Classification:

438243, 438404

Abstract:

A method for removing surface oxide from polysilicon includes depositing a very thin layer of germanium (e. g. monolayers in thickness) over the polysilicon immediately before a subsequent polysilicon deposition step, and then heating the germanium-coated polysilicon in a vacuum to sublime (remove) volatile germanium oxide. This method is applied to formation of a trench capacitor, which uses either doped amorphous silicon or doped amorphous SiGe material in the formation of the electrodes.

US Patent:

6528383, Mar 4, 2003

Filed:

Dec 12, 2001

Appl. No.:

10/016016

Inventors:

Satya N. Chakravarti - Hopewell Junction NY
Ashima B. Chakravarti - Hopewell Junction NY
Irene L. McStay - Hopewell Junction NY
Kwong Hon Wong - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich

International Classification:

H01L 2100

US Classification:

438381, 438382, 438386

Abstract:

A compact resistor is formed in an integrated circuit using many of the same steps as are employed in forming a trench capacitor for a DRAM cell; in particular depositing a layer of heavily doped germanium in the trench interior after the step of doping the substrate to form the bottom plate for the capacitor, depositing polysilicon having the required resistivity in the trench then removing the germanium and leaving only enough to form an ohmic contact in the trench bottom.

US Patent:

6539625, Apr 1, 2003

Filed:

Jan 11, 2001

Appl. No.:

09/759017

Inventors:

Brett H. Engel - Fishkill NY
Mark Hoinkis - Fishkill NY
John A. Miller - Newburgh NY
Yun-Yu Wang - Poughquag NY
Kwong Hon Wong - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich

International Classification:

H05K 302

US Classification:

29846, 29847, 29852, 29830, 29831

Abstract:

In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Cr, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while maintaining low resistance.

US Patent:

6620657, Sep 16, 2003

Filed:

Jan 15, 2002

Appl. No.:

10/052151

Inventors:

Tricia L. Breen - Hopewell Junction NY
Lawrence A. Clevenger - LaGrangeville NY
Louis L. Hsu - Fishkill NY
Li-Kong Wang - Montvale NJ
Kwong Hon Wong - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438151, 438 99, 438164, 438455

Abstract:

A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

US Patent:

6664576, Dec 16, 2003

Filed:

Sep 25, 2002

Appl. No.:

10/254739

Inventors:

Tricia L. Breen - Hopewell Junction NY
Lawrence A. Clevenger - LaGrangeville NY
Louis L. Hsu - Fishkill NY
Li-Kong Wang - Montvale NJ
Kwong Hon Wong - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27148

US Classification:

257220

Abstract:

A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconductor body layer, and an etch stop strip positioned between a portion of the first conductive layer and the semiconductor body layer.