Lam D Ho

US Patent:

20190086946, Mar 21, 2019

Filed:

Nov 16, 2018

Appl. No.:

16/193410

Inventors:

- San Diego CA, US
Lam HO - Austin TX, US
Carlos Andres RODRIGUEZ ANCER - Austin TX, US
Bhavin SHAH - Cedar Park TX, US

International Classification:

G06F 1/03
H03K 5/131
H03K 3/012
G06F 1/08
G06F 1/10
H03K 21/40
G06F 1/32

Abstract:

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

US Patent:

20180348809, Dec 6, 2018

Filed:

Jun 5, 2017

Appl. No.:

15/614358

Inventors:

- San Diego CA, US
Lam Ho - Austin TX, US
Carlos Andres Rodriguez Ancer - Austin TX, US
Bhavin Shah - Austin TX, US

International Classification:

G06F 1/03
G06F 1/32
G06F 1/10
H03K 21/40

Abstract:

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

US Patent:

20180325743, Nov 15, 2018

Filed:

May 12, 2017

Appl. No.:

15/594262

Inventors:

- Austin TX, US
Lam Trong HO - Austin TX, US

International Classification:

A61F 13/42
A61B 5/145
A61B 5/20
G08B 21/20

Abstract:

An apparatus and a system for a smart diaper are described. These smart diapers include a disposable detection component and a reusable component including various processing circuitries. The disposable component can include a paper printed sensor pad. Paper printed sensor pads can provide for a wide detection area, and accurate determination of whether human waste is present in the diaper. Additionally, the sensor pad can determine the amount of waste exposed to the sensor pad. In certain embodiments, the sensor can also detect a temperature within the diaper. In some embodiments, the smart diapers can provide for location tracking of the wearer of the diaper, and provide notifications to the caretaker based on the location of the wearer. In some embodiments, the reusable component can be a small circular component which is mounted on the outside of the smart diapers.

US Patent:

20180284859, Oct 4, 2018

Filed:

Mar 28, 2017

Appl. No.:

15/471692

Inventors:

- San Diego CA, US
Rajeev Jain - San Diego CA, US
Sassan Shahrokhinia - San Diego CA, US
Lam Ho - Austin TX, US

International Classification:

G06F 1/26

Abstract:

An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

US Patent:

20180026805, Jan 25, 2018

Filed:

Jul 18, 2017

Appl. No.:

15/652688

Inventors:

Lam Trong Ho - Austin TX, US

International Classification:

H04L 12/18
H04L 29/08

Abstract:

Provided is method and system for synchronizing a communication appointment. The method includes synchronizing to a first user calendar. The first user calendar includes one or more identified available time slots. In some embodiments, a request for a communication appointment between a first user and the second user is received (e.g., from a second user). The request for the communication appointment includes a requested appointment time. The request for the communication appointment is processed, where the processing the request includes determining whether the requested appointment time includes at least one of the one or more identified available time slots. Based on a determination that the requested appointment time does include at least one of the one or more identified available time slots, the communication appointment between the first user and the second user is synchronized.