Lan Sum Yu

US Patent:

20220254886, Aug 11, 2022

Filed:

Feb 8, 2021

Appl. No.:

17/169916

Inventors:

- Santa Clara CA, US
El Mehdi Bazizi - San Jose CA, US
Siddarth Krishnan - San Jose CA, US
Xing Chen - Dublin CA, US
Lan Yu - Albany NY, US
Tyler Sherwood - Fonda NY, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 29/36
H01L 29/872
H01L 21/02
H01L 21/265
H01L 21/285
H01L 21/3065
H01L 29/66

Abstract:

Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

US Patent:

20230015781, Jan 19, 2023

Filed:

Jul 15, 2021

Appl. No.:

17/376504

Inventors:

- Santa Clara CA, US
Seshadri Ganguli - Sunnyvale CA, US
Lan Yu - Voorheesville NY, US
Siddarth Krishnan - Newark CA, US
Srinivas Gandikota - Santa Clara CA, US
Jacqueline S. Wrench - San Jose CA, US
Yixiong Yang - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 29/45
H01L 29/40
H01L 21/285
H01L 21/324

Abstract:

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.