Lei Chen

US Patent:

7571302, Aug 4, 2009

Filed:

Feb 4, 2005

Appl. No.:

11/050454

Inventors:

Lei Chen - Austin TX, US
David Albonesi - Ithaca NY, US
Steve Dropsho - CH1010, Lausanne, CH

International Classification:

G06F 9/00

US Classification:

712217

Abstract:

A data dependence table in RAM relates physical register addresses to instructions such that for each instruction, the registers on whose data the instruction depends are identified. The table is updated for each instruction added to the pipeline. For a branch instruction, the table identifies the registers relevant to the branch instruction for branch prediction.

US Patent:

8086831, Dec 27, 2011

Filed:

Feb 1, 2008

Appl. No.:

12/024241

Inventors:

Lei Chen - Austin TX, US
Lixin Zhang - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/35
G06F 9/355

US Classification:

712240, 712239

Abstract:

In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.

US Patent:

8255631, Aug 28, 2012

Filed:

Feb 1, 2008

Appl. No.:

12/024389

Inventors:

Lei Chen - Austin TX, US
Lixin Zhang - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 9/00

US Classification:

711137, 711E12004, 712225

Abstract:

A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.

US Patent:

8285765, Oct 9, 2012

Filed:

Dec 11, 2006

Appl. No.:

11/608907

Inventors:

Lei Chen - Austin TX, US
Hung C. Ngo - Austin TX, US
Kevin J. Nowka - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38

US Classification:

708207

Abstract:

A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value, which is the larger value. According to a second embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value. The third value is a fourth value, if the carry-out signal designates the first value as the larger value or the third value is a fifth value, if the carry-out signal designates the second value as the larger value.

US Patent:

20080126771, May 29, 2008

Filed:

Jul 25, 2006

Appl. No.:

11/459683

Inventors:

Lei Chen - Austin TX, US
Zhigang Hu - Ossining NY, US
Lixin Zhang - Austin TX, US

International Classification:

G06F 9/38

US Classification:

712238, 712E09055

Abstract:

An instruction cache (I-Cache) for a processor is configured to include a Branch Target Extension associated with each Instruction Sector. When an Instruction Sector is fetched, the Branch Target Extension is simultaneously fetched. If the Instruction Sector has a branch instruction that is predicted taken, then the branch target address in the branch extension is used to access the next Instruction Sector. In other embodiments, each Instruction Sector has a plurality of Branch Target Extensions each corresponding to a potential branch instruction in an Instruction Sector. In this case, the Branch Target Extensions are partitioned into an instruction index field for locating branch instruction in the Instruction Sector, a local predictor field for predicted taken status and a target address field for the branch target address. The least significant bits of the instruction fetch address are compared to the instruction indexes to determine a particular Branch Target Extension to use.

US Patent:

20080141046, Jun 12, 2008

Filed:

Dec 6, 2006

Appl. No.:

11/567395

Inventors:

Lei Chen - Austin TX, US
Jente B. Kuang - Austin TX, US
Brian R. Mestan - Austin TX, US
Hung C. Ngo - Austin TX, US
Kevin J. Nowka - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/32

US Classification:

713300

Abstract:

The present invention relates to a methodology for controlling the power consumption in a computing device based upon extended register file extension values, the method further comprising the steps of identifying an upper bit data register value and a lower bit data register value for a data register value, and inputting the upper bit data register value to a detect logic component, wherein the upper bit data register value is used to generate a data register extension value. The method further comprises the steps of utilizing the data register extension value as a power control signal serving to activate or deactivate a power supply signal to a segment of a data path, and updating the data register extension value in a subsequent data register write computational function.

US Patent:

20090013284, Jan 8, 2009

Filed:

Apr 17, 2008

Appl. No.:

12/105148

Inventors:

Lei Chen - Austin TX, US

Assignee:

VirSyCom, Inc. - Lakeway TX

International Classification:

G06F 3/048

US Classification:

715810

Abstract:

Methods and systems for communicating information are disclosed, including creating sequence instructions configured to define a set of permitted sequences for a plurality of documents. The sequence instructions may be sent to a user and interpreted using an active user interface for the user to select one or more sequences from the set of permitted sequences. The plurality of documents may then be executed in response to the selecting one or more of the sequences.

US Patent:

20100031011, Feb 4, 2010

Filed:

Aug 4, 2008

Appl. No.:

12/185776

Inventors:

Lei Chen - Austin TX, US
David S. Levitan - Austin TX, US
David Mui - Round Rock TX, US
Robert A. Philhower - Valley Cottage NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/30

US Classification:

712240, 712E09016

Abstract:

The invention relates to a method and apparatus for controlling the instruction flow in a computer system and more particularly to the predicting of outcome of branch instructions using branch prediction arrays, such as BHTs. In an embodiment, the invention allows concurrent BHT read and write accesses without the need for a multi-ported BHT design, while still providing comparable performance to that of a multi-ported BHT design.