Li Lien Wang

US Patent:

8010931, Aug 30, 2011

Filed:

Feb 26, 2007

Appl. No.:

11/678994

Inventors:

Matthew C. French - Falls Church VA, US
Li Wang - Boise ID, US
Deepak Agarwal - Austin TX, US
Azadeh Davoodi - Madison WI, US

Assignee:

University of Southern California - Los Angeles CA

International Classification:

G06F 17/50

US Classification:

716133, 716132, 716134, 716135, 703 14

Abstract:

A configurable logic tool that allows minimization of dynamic power within an FPGA design without changing user-entered specifications. The minimization of power may use minimized clock nets as a first order operation, and a second order operation that minimizes other factors, such as area of placement, area of clocks and/or slack.

US Patent:

57824037, Jul 21, 1998

Filed:

Jan 6, 1997

Appl. No.:

8/779868

Inventors:

Li Wang - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B23K 1018

US Classification:

228264

Abstract:

A device for removal of a semiconductor chip interconnected to a substrate package via solder ball connections, for instance, includes an ultrasonic transducer for providing lateral ultrasonic vibration. A converter is coupled between the ultrasonic transducer and semiconductor chip for converting the lateral ultrasonic vibration to a torsional ultrasonic vibration, wherein the torsional ultrasonic vibration is perpendicular to the lateral ultrasonic vibration. The lateral-to-torsional converter further applies the torsional ultrasonic vibration to the chip for facilitating its removal from the substrate package. A method for removal of a semiconductor chip interconnected to a substrate package is also disclosed.