Li I Wang

US Patent:

8010931, Aug 30, 2011

Filed:

Feb 26, 2007

Appl. No.:

11/678994

Inventors:

Matthew C. French - Falls Church VA, US
Li Wang - Boise ID, US
Deepak Agarwal - Austin TX, US
Azadeh Davoodi - Madison WI, US

Assignee:

University of Southern California - Los Angeles CA

International Classification:

G06F 17/50

US Classification:

716133, 716132, 716134, 716135, 703 14

Abstract:

A configurable logic tool that allows minimization of dynamic power within an FPGA design without changing user-entered specifications. The minimization of power may use minimized clock nets as a first order operation, and a second order operation that minimizes other factors, such as area of placement, area of clocks and/or slack.

US Patent:

57310319, Mar 24, 1998

Filed:

Dec 20, 1995

Appl. No.:

8/575862

Inventors:

Raghu Nath Bhattacharya - Littleton CO
Rommel Noufi - Golden CO
Li Wang - Golden CO

Assignee:

Midwest Research Institute - Kansas City MO

International Classification:

H01L 3118

US Classification:

427 76

Abstract:

A process for chemical bath deposition of selenide and sulfide salts as films and powders employable as precursors for the fabrication of solar cell devices. The films and powders include (1) Cu. sub. x Se. sub. n, wherein x=1-2 and n=1-3; (2) Cu. sub. x Ga. sub. y Se. sub. n, wherein x=1-2, y=0-1 and n=1-3; (3) Cu. sub. x In. sub. y Se. sub. n, wherein x=1-2. 27, y=0. 72-2 and n=1-3; (4) Cu. sub. x (InGa). sub. y Se. sub. n, wherein x=1-2. 17, y=0. 96-2 and n=1-3; (5) In. sub. y Se. sub. n, wherein y=1-2. 3 and n=1-3; (6) Cu. sub. x S. sub. n, wherein x=1-2 and n=1-3; and (7) Cu. sub. x (InGa). sub. y (SeS). sub. n, wherein x=1-2, y=0. 07-2 and n=0. 663-3. A reaction vessel containing therein a substrate upon which will form one or more layers of semiconductor material is provided, and relevant solution mixtures are introduced in a sufficient quantity for a sufficient time and under favorable conditions into the vessel to react with each other to produce the resultant salt being prepared and deposited as one or more layers on the substrate and as a powder on the floor of the vessel. Hydrazine is present during all reaction processes producing non-gallium containing products and optionally present during reaction processes producing gallium-containing products to function as a strong reducing agent and thereby enhance reaction processes.

US Patent:

52927075, Mar 8, 1994

Filed:

Nov 25, 1992

Appl. No.:

7/981702

Inventors:

Luis M. Aparicio - Madison WI
Scott R. Keenan - Dover NJ
Li Wang - Bloomingdale IL

Assignee:

Allied-Signal Inc. - Morris Township, Morris County NJ

International Classification:

C01B 3102
C01B 3108
B01J 2030
B01J 2020

US Classification:

502418

Abstract:

Natural gas is stored in a closed vessel under a pressure of about 1400 to 4500 kPa using a carbon molecular sieve adsorbent. The deliverable volume of natural gas from a vessel packed with carbon molecular sieve particles is increased by raising the density of the polymer precursor of the carbon molecular sieve through adjustment of the conditions for suspension polymerization of vinylidene chloride.

US Patent:

57824037, Jul 21, 1998

Filed:

Jan 6, 1997

Appl. No.:

8/779868

Inventors:

Li Wang - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B23K 1018

US Classification:

228264

Abstract:

A device for removal of a semiconductor chip interconnected to a substrate package via solder ball connections, for instance, includes an ultrasonic transducer for providing lateral ultrasonic vibration. A converter is coupled between the ultrasonic transducer and semiconductor chip for converting the lateral ultrasonic vibration to a torsional ultrasonic vibration, wherein the torsional ultrasonic vibration is perpendicular to the lateral ultrasonic vibration. The lateral-to-torsional converter further applies the torsional ultrasonic vibration to the chip for facilitating its removal from the substrate package. A method for removal of a semiconductor chip interconnected to a substrate package is also disclosed.