Ljubo Radic

US Patent:

7919388, Apr 5, 2011

Filed:

Nov 30, 2009

Appl. No.:

12/627739

Inventors:

Ljubo Radic - Chandler AZ, US
Edouard D. de Frésart - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/72

US Classification:

438424, 438270, 438296, 438435

Abstract:

Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.

US Patent:

8502287, Aug 6, 2013

Filed:

Oct 12, 2010

Appl. No.:

12/902805

Inventors:

Ljubo Radic - Chandler AZ, US
Edouard D. de Frésart - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/78

US Classification:

257288, 257330, 257333, 257773

Abstract:

Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.

US Patent:

20090294843, Dec 3, 2009

Filed:

May 30, 2008

Appl. No.:

12/129846

Inventors:

Ljubo Radic - Chandler AZ, US
Edouard D. deFresart - Tempe AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 21/3205
H01L 29/78

US Classification:

257330, 438589, 257E29262, 257E2141

Abstract:

Field effect devices and ICs () with very low gate-drain capacitance Cgd are provided by forming a substantially empty void () between the gate (′) and the drain () regions. For vertical FETS a cavity () is etched in the semiconductor (SC) () and provided with a gate dielectric liner (). A poly-SC gate (′) deposited in the cavity () has a central fissure (empty pipe) () extending through to the underlying SC (). This fissure () is used to etch the void () in the SC () beneath the poly-gate (′). The fissure () is then closed by a dielectric plug () formed by deposition or oxidation without significantly filling the etched void (). Conventional process steps are used to provide the source () and body regions () around the cavity () containing the gate (′), and to provide a drift space () and drain region () below the body region (). The etched void () between the gate (′) and drain () provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.

US Patent:

20110147835, Jun 23, 2011

Filed:

Feb 24, 2011

Appl. No.:

13/034084

Inventors:

Ljubo Radic - Chandler AZ, US
Edouard D. de Frésart - Tempe AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 29/78

US Classification:

257333, 257E29262

Abstract:

Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface.

US Patent:

20220406906, Dec 22, 2022

Filed:

Jun 17, 2021

Appl. No.:

17/350040

Inventors:

- AUSTIN TX, US
James Albert Kirchgessner - Tempe AZ, US
Ljubo Radic - Gilbert AZ, US

International Classification:

H01L 29/417
H01L 29/45
H01L 29/735
H01L 29/40
H01L 29/66

Abstract:

A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.

US Patent:

20210305385, Sep 30, 2021

Filed:

Mar 31, 2020

Appl. No.:

16/836344

Inventors:

- AUSTIN TX, US
Bernhard Grote - Phoenix AZ, US
Ljubo Radic - Gilbert AZ, US

International Classification:

H01L 29/423
H01L 29/78
H01L 29/40
H01L 29/66

Abstract:

A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.

US Patent:

20210159319, May 27, 2021

Filed:

Nov 22, 2019

Appl. No.:

16/692126

Inventors:

- AUSTIN TX, US
Bernhard Grote - Phoenix AZ, US
Ljubo Radic - Gilbert AZ, US

International Classification:

H01L 29/40
H01L 29/10
H01L 29/45
H01L 29/78
H01L 21/765
H01L 29/66

Abstract:

A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.

US Patent:

20210159323, May 27, 2021

Filed:

Nov 22, 2019

Appl. No.:

16/692517

Inventors:

- AUSTIN TX, US
Ljubo Radic - Gilbert AZ, US
Bernhard Grote - Phoenix AZ, US

International Classification:

H01L 29/66
H01L 29/40
H01L 27/088
H01L 29/78

Abstract:

Disclosed herein is a transistor structure that is formed by forming a sidewall spacer along a first vertical component sidewall of a trench wherein no sidewall spacer is formed along a second vertical component sidewall of the trench. During an etching of a dielectric layer in the trench, the sidewall spacer protects a first portion of the dielectric layer from being etched while a second portion of the dielectric layer along the second sidewall is etched. A portion of a control terminal can be formed in the space where the second portion is removed.