Man Man Wong

US Patent:

8138914, Mar 20, 2012

Filed:

May 8, 2009

Appl. No.:

12/463355

Inventors:

Man Kit Wong - Los Altos CA, US
Ivan C. Eng - Santa Clara CA, US

International Classification:

G08B 1/08

US Classification:

34053913, 34053911, 34028601

Abstract:

A method and a system for securing a device in a single embodiment or in some embodiments, the system comprises a remote module which comprises a switch electrically connected to an electrical input or at electrical output of the device, a serial link comprising a first attribute and configured to connect to at least some of the plurality of portions of the device, and a panel control logic module operatively coupled to the switch, wherein the panel control logic module is configured to issue a first instruction to actuate the switch based at least in part upon a result of checking the first attribute of the serial link. In the single embodiment or in some embodiments, the system comprises a control center comprising a command control logic module and a communication interface configured for wired or wireless communication between the control center and the remote module.

US Patent:

52504646, Oct 5, 1993

Filed:

Mar 11, 1992

Appl. No.:

7/850192

Inventors:

Man Wong - Dallas TX
David K. Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2114

US Classification:

437170

Abstract:

A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse. The method of forming the antifuse structure comprises the steps of forming a pedestal having a sidewall comprising a first layer of electrically conductive material and a first electrically insulating layer thereon, forming a conformal layer of electrically conductive material on the pedestal and exposed substrate extending along the sidewall, forming a sidewall insulating layer along the sidewall portion of the layer of electrically conductive material, removing all of the exposed portion of the layer of electrically conductive material while retaining the portion of the layer of electrically conductive material between the pedestal and the sidewall insulating layer, forming a second layer of electrically insulating material over the structure, and forming a second layer of electrically conductive material over the second layer of electrically insulating material.

US Patent:

54239443, Jun 13, 1995

Filed:

Mar 11, 1994

Appl. No.:

8/184801

Inventors:

Man Wong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

1566461

Abstract:

A method for etching a silicon wafer (20) by using hydrogen fluoride and water vapor combined with ozone is disclosed. The process does not require additional energy excitation or high pressure.

US Patent:

53714024, Dec 6, 1994

Filed:

Mar 22, 1994

Appl. No.:

8/215881

Inventors:

Man Wong - Dallas TX
David K. Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702

US Classification:

257530

Abstract:

A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse. The method of forming the antifuse structure comprises the steps of forming a pedestal having a sidewall comprising a first layer of electrically conductive material and a first electrically insulating layer thereon, forming a conformal layer of electrically conductive material on the pedestal and exposed substrate extending along the sidewall, forming a sidewall insulating layer along the sidewall portion of the layer of electrically conductive material, removing all of the exposed portion of the layer of electrically conductive material while retaining the portion of the layer of electrically conductive material between the pedestal and the sidewall insulating layer, forming a second layer of electrically insulating material over the structure, and forming a second layer of electrically conductive material over the second layer of electrically insulating material.

US Patent:

51703726, Dec 8, 1992

Filed:

Apr 15, 1992

Appl. No.:

7/870158

Inventors:

Man Wong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140

US Classification:

257304

Abstract:

A memory device having an array of memory cells each including a trench capacitor and a pass transistor. The transistor has its source connected to the storage capacitor, its drain connected to a bit line, and its gate connected to a word line. The bit line is formed over a field oxide layer formed on the semiconductor substrate so there is minimal contact between the bit line and the semiconductor substrate. The storage dielectric in the trench is recessed from the surface of the semiconductor substrate.

US Patent:

58800310, Mar 9, 1999

Filed:

Jun 25, 1992

Appl. No.:

7/904419

Inventors:

Man Wong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2130

US Classification:

438706

Abstract:

A controlled amount of gaseous nitrogen (12) is passed over a heated azeotropic solution of hydrogen fluoride and water (16) and producing an hydrogen fluoride vapor. The hydrogen fluoride vapor is combined with gaseous hydrogen chloride (14) and then the wafers (20) are exposed to the combined vapor at low pressure and room temperature.

US Patent:

56129149, Mar 18, 1997

Filed:

Jan 6, 1993

Appl. No.:

8/001004

Inventors:

David K. Liu - Dallas TX
Man Wong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1300

US Classification:

36518526

Abstract:

A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

US Patent:

56747640, Oct 7, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/482099

Inventors:

David K. Liu - Dallas TX
Man Wong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265
H01L 218247

US Classification:

437 35

Abstract:

A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).