Manuel Jacobo Mejia

US Patent:

6335634, Jan 1, 2002

Filed:

May 22, 2000

Appl. No.:

09/577297

Inventors:

Srinivas T. Reddy - Fremont CA 94539
Ketan Zaveri - San Jose CA 95129
Christopher F. Lane - Campbell CA 95008
Andy L. Lee - San Jose CA 95131
Cameron R. McClintock - Mountain View CA 94043
Bruce B. Pedersen - San Jose CA 95136
Manuel Mejia - San Jose CA 95116
Richard G. Cliff - Milpitas CA 95116

International Classification:

G06F 738

US Classification:

326 41, 326 40, 326 39, 326 38

Abstract:

Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

US Patent:

6344755, Feb 5, 2002

Filed:

Oct 18, 2000

Appl. No.:

09/691424

Inventors:

Srinivas T. Reddy - Fremont CA
Manuel Mejia - San Jose CA
Andy L. Lee - San Jose CA
Bruce B. Pedersen - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19003

US Classification:

326 10, 326 38, 326 39

Abstract:

A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows.

US Patent:

6392954, May 21, 2002

Filed:

Dec 21, 2000

Appl. No.:

09/747191

Inventors:

Srinivas T. Reddy - Fremont CA
Christopher F. Lane - Campbell CA
Manuel Mejia - San Jose CA
Richard G. Cliff - Milpitas CA
Kerry Veenstra - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 800

US Classification:

36523005, 36518902, 36523002

Abstract:

A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.

US Patent:

6417694, Jul 9, 2002

Filed:

Sep 19, 2001

Appl. No.:

09/956748

Inventors:

Srinivas T. Reddy - Fremont CA
Richard G. Cliff - Milpitas CA
Christopher F. Lane - Campbell CA
Ketan H. Zaveri - San Jose CA
Manuel M. Mejia - San Jose CA
David Jefferson - San Jose CA
Bruce B. Pedersen - San Jose CA
Andy L. Lee - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39

Abstract:

A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e. g.

US Patent:

6480028, Nov 12, 2002

Filed:

Feb 1, 2002

Appl. No.:

10/062741

Inventors:

David E. Jefferson - San Jose CA
Cameron McClintock - Mountain View CA
James Schleicher - Santa Clara CA
Andy L. Lee - San Jose CA
Manuel Mejia - San Jose CA
Bruce B. Pederson - San Jose CA
Christopher F. Lane - Campbell CA
Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 40

Abstract:

A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

US Patent:

6577160, Jun 10, 2003

Filed:

Jun 10, 2002

Appl. No.:

10/170026

Inventors:

Srinivas T. Reddy - Fremont CA
Richard G. Cliff - Milpitas CA
Christopher F. Lane - Campbell CA
Ketan H. Zaveri - San Jose CA
Manuel M. Mejia - San Jose CA
David Jefferson - San Jose CA
Bruce B. Pedersen - San Jose CA
Andy L. Lee - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39

Abstract:

A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e. g. , for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

US Patent:

6798242, Sep 28, 2004

Filed:

Apr 29, 2003

Appl. No.:

10/426991

Inventors:

Srinivas T. Reddy - Fremont CA
Richard G. Cliff - Milpitas CA
Christopher F. Lane - Campbell CA
Ketan H. Zaveri - San Jose CA
Manuel M. Mejia - San Jose CA
David Jefferson - San Jose CA
Bruce B. Pedersen - San Jose CA
Andy L. Lee - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39

Abstract:

A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e. g.

US Patent:

6879183, Apr 12, 2005

Filed:

Sep 27, 2002

Appl. No.:

10/260712

Inventors:

David E. Jefferson - San Jose CA, US
Cameron McClintock - Mountain View CA, US
James Schleicher - Santa Clara CA, US
Andy L. Lee - San Jose CA, US
Manuel Mejia - San Jose CA, US
Bruce B. Pedersen - San Jose CA, US
Christopher F. Lane - San Jose CA, US
Richard G. Cliff - Milpitas CA, US
Srinivas T. Reddy - Fremont CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K019/177

US Classification:

326 41, 326 47

Abstract:

A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.