Mark L Dean

US Patent:

6336170, Jan 1, 2002

Filed:

Oct 13, 1998

Appl. No.:

09/170898

Inventors:

Mark E. Dean - Austin TX
James Michael Magee - Fernandina Beach FL
Ronald Lynn Rockhold - Austin TX
James Van Fleet - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711147

Abstract:

A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory location included within a shared-memory included within each of the plurality of nodes by each of the plurality of nodes. The operating system processes a designated application utilizing the plurality of nodes. During the processing, for each of the plurality of nodes, a determination is made of a quantity of times each memory location included within a shared-memory included within each of the plurality of nodes is accessed by each of the plurality of nodes.

US Patent:

6338122, Jan 8, 2002

Filed:

Dec 15, 1998

Appl. No.:

09/211351

Inventors:

Yoanna Baumgartner - Austin TX
Mark Edward Dean - Austin TX
Anna Elman - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141, 711100, 711124, 711147, 711154

Abstract:

A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

US Patent:

6566921, May 20, 2003

Filed:

Aug 3, 2000

Appl. No.:

09/631718

Inventors:

David William Boerstler - Round Rock TX
Mark Edward Dean - Austin TX
Hung Cai Ngo - Austin TX
Andrew Christian Zimmerman - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03L 706

US Classification:

327156, 327117

Abstract:

An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.

US Patent:

6522207, Feb 18, 2003

Filed:

Aug 3, 2000

Appl. No.:

09/631720

Inventors:

David William Boerstler - Round Rock TX
Mark Edward Dean - Austin TX
Hung Cai Ngo - Austin TX
Andrew Christian Zimmerman - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03L 700

US Classification:

331 25, 331 1 A, 331 74, 327156

Abstract:

An apparatus and a method for making small frequency adjustments in a frequency synthesizer. The frequency synthesizer consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and the output of the forward portion of the phase locked loop connected to a dynamically variable frequency divider. By changing the constant of division in the variable frequency divider, the output of the frequency divider can be rapidly changed in small increments. The dynamically variable frequency divider is key to this design. This digital circuit stores the current divisor value and has an input for a new divisor value. When a signal is sent to switch to the new divisor value, the circuit uses an incrementer and associated logic to rapidly change to the new constant of division.

US Patent:

6763474, Jul 13, 2004

Filed:

Aug 3, 2000

Appl. No.:

09/631712

Inventors:

David William Boerstler - Round Rock TX
Mark Edward Dean - Austin TX
Hung Cai Ngo - Austin TX
Andrew Christian Zimmerman - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06P 112

US Classification:

713400, 713503, 375376

Abstract:

An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a âtime of dayâ value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.

US Patent:

60818743, Jun 27, 2000

Filed:

Sep 29, 1998

Appl. No.:

9/162828

Inventors:

Gary Dale Carpenter - Pflugerville TX
Mark Edward Dean - Austin TX
David Brian Glasco - Austin TX
Richard Nicholas Iachetta - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

711141

Abstract:

A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

US Patent:

60887508, Jul 11, 2000

Filed:

Feb 10, 1999

Appl. No.:

9/247536

Inventors:

Daniel Paul Beaman - Austin TX
Gary Dale Carpenter - Pflugerville TX
Mark Edward Dean - Austin TX
Wendel Glenn Voigt - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1336

US Classification:

710107

Abstract:

A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master. Thereafter, in response to a signal transmitted from an arbitration control unit to the first bus master instructing the first bus master to terminate its bus transactions, control of the bus is granted to the second bus master.

US Patent:

56030410, Feb 11, 1997

Filed:

Dec 13, 1994

Appl. No.:

8/354696

Inventors:

Gary D. Carpenter - Pflugerville TX
Mark E. Dean - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395800

Abstract:

A method and system are disclosed for reading data from an m-byte memory device utilizing a processor having an n-byte data bus, where m is less than or equal to n, which do not require the processor to support special bus cycles, bus select signals, or dynamic bus sizing. Responsive to an initiating signal from the processor to an interface controller, a plurality of data latches are initialized by a control signal. An address counter is also initialized. The memory device is activated by a control signal. Latching of data by one of the plurality of data latches is enabled. Data associated with an address indicated by the address counter is then latched from the memory device utilizing the enabled data latch. The address counter is incremented. The enabling, latching, and incrementing steps are repeated until n bytes of data are latched.