Mark A Mcclain

US Patent:

6601167, Jul 29, 2003

Filed:

Jan 14, 2000

Appl. No.:

09/483318

Inventors:

Ralph E. Gibson - Campbell CA
Loren J. Shalinsky - Mountain View CA
Mark A. McClain - San Diego CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9445

US Classification:

713 2, 713 1

Abstract:

A computer system includes a processor and a sequential access memory having a boot program stored therein. A boot loader includes a state machine which, in response to initialization of the computer system, controls the sequential access memory to read the boot program and then controls the processor to jump to the boot program in the sequential access memory. The first memory page of the boot program causes further boot code to be transferred to a Random Access Memory (RAM). The processor then jumps to the code in the RAM, which causes the remainder of the boot code to be transferred from the sequential access memory to the RAM and executed.

US Patent:

6731536, May 4, 2004

Filed:

Mar 7, 2002

Appl. No.:

10/091767

Inventors:

Mark Alan McClain - San Diego CA
Michael Garrett Tanaka - San Jose CA
Ralf Muenster - Los Altos CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

36518504, 36518529, 36518901, 365218

Abstract:

In protecting Flash memory data, a flexible system and method provides for different levels of protection. It offers the ability to dynamically lock a sector of memory using a dynamic protection bit in volatile memory. It offers persistent locking of a sector using a non-volatile bit in memory and locking this status using a lock bit in volatile memory. It offers yet further protection by including a password mode which requires a password to clear the lock bit. The password is located in an unreadable, one time programmable area of the memory. The memory also includes areas, whose protection state is controlled by an input signal, for storing boot code in a protected manner.

US Patent:

7058779, Jun 6, 2006

Filed:

Mar 5, 2002

Appl. No.:

10/091766

Inventors:

Mark Alan McClain - San Diego CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711170, 711100, 711104, 711105, 711111, 711112, 711169, 713 1, 713 2, 710 10

Abstract:

A method for reducing the number of interface lines and non-volatile memory devices in a computer system includes providing a non-volatile memory having a SDRAM style interface. A system having both non-volatile memory and SDRAM has reduced interface lines by providing only one memory interface. A system where the SDRAM interface logic is initialized by code stored in the non-volatile memory having a SDRAM style interface, eliminating any requirement for other non-volatile memory, independent of the SDRAM interface, from which to initialize the system.

US Patent:

7443712, Oct 28, 2008

Filed:

Sep 7, 2006

Appl. No.:

11/470958

Inventors:

Colin Bill - Cupertino CA, US
Mark McClain - San Diego CA, US
Michael VanBuskirk - Saratoga CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 11/00

US Classification:

365148, 365163, 365204

Abstract:

A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.

US Patent:

7781806, Aug 24, 2010

Filed:

Apr 18, 2008

Appl. No.:

12/106180

Inventors:

Michael VanBuskirk - Saratoga CA, US
Mark McClain - San Diego CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 27/148

US Classification:

257225, 257 98, 257324, 257462, 257E27127, 438 24, 438 29

Abstract:

A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell.

US Patent:

20060095622, May 4, 2006

Filed:

Oct 28, 2004

Appl. No.:

10/975629

Inventors:

Stephan Rosner - Campbell CA, US
Mark McClain - San Diego CA, US
Eugen Gershon - San Jose CA, US

International Classification:

G06F 13/00

US Classification:

710107000

Abstract:

A system and method are disclosed for improved memory performance in a mobile device. A mobile device incorporating teachings disclosed herein may include, for example, a central processing unit (CPU) residing on a first chip. The mobile device may also include a memory system residing on a second chip. The memory system may include, for example, a memory controller and at least one type of memory combined in a single multi-chip package. The multi-chip package may effectively internalize higher pin count interfaces interconnecting the memory controller and the at least one type of memory. With some implementations, a high frequency, low pin-count external bus may form at least a portion of a link communicatively coupling the multi-chip package and the CPU. In practice, the high frequency, low pin-count external bus may physically connect to a bus interface residing on the first chip. The bus interface may be communicatively coupled to the CPU via an internal CPU bus also located on the first chip. In operation, the bus interface may provide bus translation between the high frequency, low pin-count external bus, and the internal CPU bus.

US Patent:

20160307611, Oct 20, 2016

Filed:

Feb 24, 2016

Appl. No.:

15/052709

Inventors:

- San Jose CA, US
Mark Alan McClain - San Diego CA, US

International Classification:

G11C 8/00

Abstract:

Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.

US Patent:

20140177375, Jun 26, 2014

Filed:

Dec 21, 2012

Appl. No.:

13/725415

Inventors:

- Sunnyvale CA, US
Mark A. McClain - San Diego CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 8/00

US Classification:

36523001

Abstract:

Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.