Maurice L Richard

US Patent:

7112990, Sep 26, 2006

Filed:

Jan 16, 2004

Appl. No.:

10/759756

Inventors:

Steven M. Waldstein - Scarborough ME, US
Maurice Richard - Gorham ME, US
Alexander Alexeyev - Yarmouth ME, US
David Reynolds - Scarborough ME, US

Assignee:

Tundra Semiconductor Corp.

International Classification:

H03K 17/16
G11C 5/14

US Classification:

326 32, 326 33, 326 34, 327530, 327534, 327157

Abstract:

Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

US Patent:

7355467, Apr 8, 2008

Filed:

Aug 14, 2006

Appl. No.:

11/504400

Inventors:

Steven M. Waldstein - Scarborough ME, US
Maurice Richard - Gorham ME, US
Alexander Alexeyev - Yarmouth ME, US
David Reynolds - Scarborough ME, US

Assignee:

Tundra Semiconductor Corporation - Ottawa

International Classification:

G11C 5/14

US Classification:

327530, 327534, 327157

Abstract:

Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

US Patent:

20120262233, Oct 18, 2012

Filed:

Apr 12, 2012

Appl. No.:

13/445590

Inventors:

Maurice B. Richard - Gorham ME, US

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

H03G 3/20

US Classification:

330129

Abstract:

This document discusses, among other things, apparatus and methods for providing dynamic range compression. In an example, an amplifier can an first amplifier configured to receive a representation of an input signal and provide an amplified representation of the input signal to an output stage, an automatic gain control comparator configured to provide automatic gain control information to the first amplifier, a plurality of dynamic range compression comparators configured to provide a plurality of signals indicative of an amplitude of an output signal of the output stage, a first voltage divider configured to provide an automatic gain control threshold to the automatic gain control comparator, and a second voltage divider configured to receive the automatic gain control threshold and to provide a plurality of range compression thresholds to the plurality of dynamic range compression comparators.

US Patent:

48603252, Aug 22, 1989

Filed:

Jun 24, 1988

Appl. No.:

7/212213

Inventors:

Percy R. Aria - Sunnyvale CA
Maurice B. Richard - Westbrook ME

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 2140

US Classification:

377 29

Abstract:

A method and apparatus for testing operation of an n-bit counter with carry inputs in an electronic system. The n-bit counter is divided into a high section and a low section. An external carry is forced to the lowest significant bit of the high section. All states of both sections of the counter are clocked, each state of each of the sections being clocked simultaneously with a corresponding state of the other of the sections. The natural carry is selected so that, at the next clock cycle, when the low section is set at the highest count, the highest significant bit of the low section is carried to the lowest significant bit of the high section.