Michael J Azevedo

US Patent:

6496878, Dec 17, 2002

Filed:

Nov 3, 1999

Appl. No.:

09/432661

Inventors:

Michael Joseph Azevedo - San Jose CA
Roger Gregory Hathorn - Tucson AZ
Andrew Dale Walls - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

710 22, 710 15, 710 20, 710 48, 710 64, 711150, 711169

Abstract:

A Transfer Progress Alert Module and a method for optimizing processing of a data transfer load, in a data communication system is provided. The data transfer load is divided in individual data blocks. The device and method simultaneously perform pipelined operations on different individual data blocks, thus optimizing the overlap of pipelined operations. The method includes initializing the transfer by selecting a pre-defined individual data block size and determining a key for selecting and monitoring transfers with transfer addresses within a pre-determined address region. The method then continuously repeats following steps until all monitored individual data blocks from the data transfer load are processed. First, the incoming individual data blocks are transferred on a bus between a peripheral device and a memory, and the Transfer Progress Alert module is used for monitoring the individual data blocks having transfer addresses determined to belong in the pre-determined address region. The TPA module is used to determine when each monitored transferred individual data block is ready for a post-processing operation, at least one post-processing operation is performed on the data, and the processed data is transferred to a peripheral device.

US Patent:

6496890, Dec 17, 2002

Filed:

Dec 3, 1999

Appl. No.:

09/454681

Inventors:

Michael Joseph Azevedo - San Jose CA 95120-4246
Brent Cameron Beardsley - Tuscon AZ 85718
Bitwoded Okbay - Gilroy CA 95020
Carol Spanel - San Jose CA 95119
Andrew Dale Walls - San Jose CA 95139

International Classification:

G06F 1300

US Classification:

710110, 710107, 710108, 710109, 710240

Abstract:

A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus. The control code is used for monitoring and controlling the circuitry and terminating the transfer in progress causing the shared bus hang-up. During the bus recovery the circuitry prevents bus request grants to the master attached to the external bus until the master subsequent reset, and the control program instructions initiates transfers for all pending requests for the shared bus from the control master queue.

US Patent:

6519666, Feb 11, 2003

Filed:

Oct 5, 1999

Appl. No.:

09/412990

Inventors:

Michael Joseph Azevedo - San Jose CA
Carol Spanel - San Jose CA
Andrew Dale Walls - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13368

US Classification:

710120, 710243, 710309

Abstract:

A shared bus arbitration scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and resources, some resources having higher priority than the others and including a peripheral device. Each master may request control of the shared bus and is adapted to perform short transfers and long burst transfers on the shared bus between a resource and the master. A shared bus arbiter is utilized for dynamically determining the highest priority request between a number of shared bus requests, and granting control of the shared bus to the highest priority requesting bus master. The arbiter utilizes a three-level priority hierarchy arbitration scheme where the highest priority level is given to short message transfer requests on the higher-priority system resources, the intermediate priority level is given to short message transfer requests on the lower-priority system resources, if there are no outstanding higher priority level requests, and the lowest priority level is given for long burst transfers, if there are no outstanding short message transfer requests.

US Patent:

6606677, Aug 12, 2003

Filed:

Mar 7, 2000

Appl. No.:

09/520876

Inventors:

Bitwoded Okbay - Gilroy CA
Andrew Dale Walls - San Jose CA
Michael Joseph Azevedo - San Jose CA

Assignee:

international Business Machines Corporation - Armonk NY

International Classification:

G06F 1324

US Classification:

710262, 710260, 710266, 710269

Abstract:

A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler. The circuitry consists of a status register where an appropriate bit is set when an interrupt is received from an external interrupt source device, and an interrupt mask register which enables and disables certain interrupts. The control code is used for monitoring and controlling the circuitry and servicing the interrupts received by the processor.

US Patent:

7035979, Apr 25, 2006

Filed:

May 22, 2002

Appl. No.:

10/154380

Inventors:

Michael Joseph Azevedo - San Jose CA, US
Andrew Dale Walls - San Jose CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711137, 711144

Abstract:

A method and apparatus for increasing the performance of a computing system and increasing the hit ratio in at least one non-L1 cache. A caching assistant and a processor are embedded in a processing system. The caching assistant analyzes system activity, monitors and coordinates data requests from the processor, processors and other data accessing devices, and monitors and analyzes data accesses throughout the cache hierarchy. The caching assistant is provided with a dedicated cache for storing fetched and prefetched data. The caching assistant improves the performance of the computing system by anticipating which data is likely to be requested for processing next, accessing and storing that data in an appropriate non-L1 cache prior to the data being requested by processors or data accessing devices. A method for increasing the processor performance includes analyzing system activity and optimizing a hit ratio in at least one non-L1 cache. The caching assistant performs processor data requests by accessing caches and monitoring the data requests to determine knowledge of the program code currently being processed and to determine if patterns of data accession exist.

US Patent:

7073030, Jul 4, 2006

Filed:

May 22, 2002

Appl. No.:

10/153966

Inventors:

Michael Joseph Azevedo - San Jose CA, US
Carol Spanel - San Jose CA, US
Andrew Dale Walls - San Jose CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711136, 711134, 711137, 711141, 711144, 711145, 711146, 711160

Abstract:

A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined based upon the parameter indicating data selection characteristics.

US Patent:

7136400, Nov 14, 2006

Filed:

Jun 21, 2002

Appl. No.:

10/177222

Inventors:

Michael Joseph Azevedo - San Jose CA, US
Andrew Dale Walls - San Jose CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 3/04
H04J 3/16
H04L 12/50
H04L 12/28

US Classification:

370535, 370466, 370366, 370426

Abstract:

Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

US Patent:

7231501, Jun 12, 2007

Filed:

Mar 30, 2004

Appl. No.:

10/813519

Inventors:

Michael J. Azevedo - San Jose CA, US
Carol Spanel - San Jose CA, US
Andrew D. Walls - San Jose CA, US

Assignee:

IBM Corporation - Armonk NY

International Classification:

G06F 13/00
G06F 11/00

US Classification:

711156, 711154, 709223, 709226, 714 47, 714 49, 710 5

Abstract:

A data initiator device designates an initial data tag set for tagging data transfers to thereby attach data tags from the designated set to commands directed to data transfers between the data initiator device and a data target device subsequent to the designation of the initial data tag set. The data transfer commands are issued with the attached data tags from the designated data tag set until an occurrence of a reset error associated with one of the issued data transfer commands. In response to the reset error, the data initiator device designates a different data tag set for tagging data transfers to thereby attach data tags from the newly designated data tag set to commands directed to data transfers between the data initiator device and the data target device subsequent to the designation of the new data tag set.