Michael W Case

US Patent:

6492873, Dec 10, 2002

Filed:

Nov 5, 2001

Appl. No.:

09/992116

Inventors:

Michael Garth Case - Thousand Oaks CA 91360

International Classification:

H03F 360

US Classification:

330286, 330295, 330306

Abstract:

The present invention describes the method and system of applying filter synthesis technique to distributed amplifier design. The method for synthesizing a distributed amplifier comprises the steps of determining an appropriate filter design characteristic, computing inductor and capacitor values, converting the equivalent values into a distributed amplifier with response characteristics that mirror that of the chosen filter. Applying filter synthesis techniques to distributed amplifier design results in predictable amplifier response characteristics. Filter synthesis techniques are used to design filters with controllable characteristics such as gain, cut-off frequency, and roll-off slope. Depending on the desired filter characteristics, appropriate inductor and capacitor sizes can be determined. Transferring these chosen inductors and capacitors sizes to the distributed amplifier results in amplitude and phase responses that behave like a preferred embodiment or prototype filter.

US Patent:

6721828, Apr 13, 2004

Filed:

Feb 25, 2002

Appl. No.:

10/082990

Inventors:

Phil Verinsky - San Jose CA
Michael Case - Los Altos Hills CA

Assignee:

Zoran Corporation - Sunnyvale CA

International Classification:

G06F 1312

US Classification:

710 62, 710 2, 710129

Abstract:

A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

US Patent:

6750709, Jun 15, 2004

Filed:

Nov 30, 2001

Appl. No.:

10/021423

Inventors:

Gopal Raghavan - Thousand Oaks CA
Michael G. Case - Carlsbad CA
Carl Pobanz - Topanga CA

Assignee:

The Boeing Company - Chicago IL

International Classification:

H03F 126

US Classification:

330149, 330124 R

Abstract:

A bipolar transistor-based linearizer with programmable gain and phase response apparatus uses a splitter to separate an incoming RF signal into two equal components: in-phase (I) and quadrature (Q, ninety degrees delayed). The I signal then passes through a first bipolar variable gain amplifier (VGA) while the Q signal passes through a second bipolar VGA. After passing through the first and second VGAs, the amplified signals are combined at the output using a summer to produce a predistorted signal that drives a TWTA. The gains of each VGA are controlled using an RF power detector in conjunction with a bipolar gain/phase slope controller. Each gain can be adjusted separately to product a large range of linearization characteristics.

US Patent:

6968404, Nov 22, 2005

Filed:

Feb 6, 2004

Appl. No.:

10/773880

Inventors:

Phil Verinsky - San Jose CA, US
Michael Case - Los Altos Hills CA, US

Assignee:

Oak Technology, Inc. - Sunnyvale CA
Zoran Corporation - Sunnyvale CA

International Classification:

G06F013/12

US Classification:

710 62, 710 2, 710129

Abstract:

A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

US Patent:

7124216, Oct 17, 2006

Filed:

Oct 19, 2005

Appl. No.:

11/254610

Inventors:

Phil Verinsky - San Jose CA, US
Michael Case - Los Altos Hills CA, US

Assignee:

Zoran Corporation - Sunnyvale CA

International Classification:

G06F 13/12

US Classification:

710 62, 710 2, 710129

Abstract:

A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

US Patent:

7124217, Oct 17, 2006

Filed:

Nov 7, 2005

Appl. No.:

11/269461

Inventors:

Phil Verinsky - San Jose CA, US
Michael Case - Los Altos Hills CA, US

Assignee:

Zoran Corporation - Sunnyvale CA

International Classification:

G06F 13/12

US Classification:

710 62, 710 2, 710129

Abstract:

A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

US Patent:

7230476, Jun 12, 2007

Filed:

Jan 18, 2005

Appl. No.:

11/039468

Inventors:

Tom Peter Edward Broekaert - Thousand Oaks CA, US
Michael Case - Thousand Oaks CA, US

Assignee:

Inphi Corporation - Westlake Village CA

International Classification:

H03B 1/00

US Classification:

327552, 327558

Abstract:

A bipolar high impedance element comprises a p-n diode made from a compound semiconductor, and circuitry arranged to reverse-bias the diode such that the diode conducts a nearly constant current—thereby enabling the element to be employed as a high impedance element. The diode is preferably the base-emitter junction of a transistor made from a compound semiconductor like InP, such that an on-chip high impedance element is provided for a fabrication process such as that used for HBTs. The element is suitably employed in an active low pass filter design: the element is connected between an input signal and an op amp input, and a feedback capacitor is connected between the op amp's output and input. The resulting filter's time constant varies with the reverse-biased diode's impedance and the capacitance of the feedback capacitor.

US Patent:

7253091, Aug 7, 2007

Filed:

Sep 26, 2002

Appl. No.:

10/256336

Inventors:

Peter D. Brewer - Westlake Village CA, US
Michael G. Case - Thousand Oaks CA, US
Andrew T. Hunter - Woodland Hills CA, US
Mehran Matloubian - Encino CA, US
John A. Roth - Ventura CA, US
Carl W. Pobanz - Rancho Palos Verdes CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 21/4763
H01L 23/34

US Classification:

438618, 438622, 438109, 438928, 438459, 257777, 257723, 257686, 257E21705

Abstract:

A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.