Michael S Chiang

US Patent:

20130266051, Oct 10, 2013

Filed:

Apr 10, 2012

Appl. No.:

13/443242

Inventors:

Michael Shih Chiang YANG - Saratoga CA, US
Lin Guo - Los Altos CA, US

International Classification:

H04B 17/00

US Classification:

375224

Abstract:

A system for parallel radio frequency (RF) testing. The system includes a plurality of signal generators, a plurality of signal analyzers, a data bus connected to the plurality of signal generators, and a controller. The controller has a connection to the data bus so as to be in electronic communication with the plurality of signal generators, and has a plurality of point to point links to respective ones of the signal analyzers so as to be in electronic communication with the plurality of signal analyzers.

US Patent:

20130266052, Oct 10, 2013

Filed:

Apr 10, 2012

Appl. No.:

13/443254

Inventors:

Michael Shih Chiang Yang - Saratoga CA, US
Lin Guo - Los Altos CA, US

International Classification:

H04B 17/00

US Classification:

375224

Abstract:

A system employing vector signal generator (VSG) and vector signal analyzer (VSA) modules or cards that are configured to test multiple devices under test simultaneously. Each VSG is configured to generate multiple RF test signals and send them to multiple devices under test simultaneously. Similarly, each VSA is configured with multiple signal receiving modules connected to a single controller or memory. Each signal receiving module receives an RF signal from a device under test, converts it to a baseband digital signal, and transmits this digital signal to the VSA's memory. A single RF testing system can employ multiple such VSGs and VSAs, each capable of evaluating multiple devices under test. Each VSG/VSA can further be tuned for operation in discrete or defined frequency bands, which are narrower than those for conventional RF testers, and which can correspond to various wireless standards.

US Patent:

47379332, Apr 12, 1988

Filed:

Feb 22, 1983

Appl. No.:

6/468602

Inventors:

Michael Chiang - Cupertino CA
John J. Zasio - Sunnyvale CA

Assignee:

Storage Technology Partners - Santa Clara CA

International Classification:

G06F 1200
G11C 800

US Classification:

364900

Abstract:

A general purpose register including two input ports and two output ports, each port being addressed by an independent addressing circuit. The general purpose register includes a number of internal registers, and the provision of four independent addresses enables data to be written into two internal registers while data is being read out of two internal registers. The general purpose register also includes circuitry for transferring data from the input ports directly to the output ports without entering the data into the internal registers. Interchanging of bytes of data input words is also accomplished by the general purpose register. The internal registers, the four independent addressing circuits, the data transferring circuitry and additional undedicated circuitry are integrated into a single chip.