Michael H Dickman

US Patent:

6732234, May 4, 2004

Filed:

Aug 7, 2000

Appl. No.:

09/633544

Inventors:

Joseph B. Rowlands - Santa Clara CA
Michael P. Dickman - San Jose CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 1200

US Classification:

711117, 711118, 711128, 711133, 711136, 711145, 711702, 711108, 711119

Abstract:

A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data. In one embodiment, the cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache.

US Patent:

6748492, Jun 8, 2004

Filed:

Aug 7, 2000

Appl. No.:

09/633690

Inventors:

Joseph B. Rowlands - Santa Clara CA
Michael P. Dickman - San Jose CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 1208

US Classification:

711128, 711137, 711133

Abstract:

A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache. The state may be altered such that a succeeding cache miss causes an eviction of the particular way. Thus, a direct access transaction may be used to provide a deterministic setting to the replacement policy, providing predictability to the entry selected to store a subsequent cache miss. In one embodiment, the replacement policy may be a pseudo-random replacement policy. In one embodiment, a direct access transaction also explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). Other embodiments may set the replacement policy based on other types of transactions.

US Patent:

6961824, Nov 1, 2005

Filed:

Jun 4, 2004

Appl. No.:

10/861638

Inventors:

Joseph B. Rowlands - Santa Clara CA, US
Michael P. Dickman - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F012/08

US Classification:

711137, 711128, 711133

Abstract:

A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache. The state may be altered such that a succeeding cache miss causes an eviction of the particular way. Thus, a direct access transaction may be used to provide a deterministic setting to the replacement policy, providing predictability to the entry selected to store a subsequent cache miss. In one embodiment, the replacement policy may be a pseudo-random replacement policy. In one embodiment, a direct access transaction also explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). Other embodiments may set the replacement policy based on other types of transactions.

US Patent:

7177986, Feb 13, 2007

Filed:

Dec 30, 2003

Appl. No.:

10/748551

Inventors:

Joseph B. Rowlands - Santa Clara CA, US
Michael P. Dickman - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 12/00

US Classification:

711144, 711118, 711128, 711134, 711135, 711 3, 711166, 714 25, 714 29, 714 30, 714 41, 714 42, 714100, 713 1, 713 2

Abstract:

A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data. In one embodiment, the cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache.