Michael J Fitzsimmons

US Patent:

6625727, Sep 23, 2003

Filed:

Nov 23, 1999

Appl. No.:

09/447253

Inventors:

William C. Moyer - Dripping Springs TX
Michael D. Fitzsimmons - Austin TX
James C. Nash - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 924

US Classification:

713 1, 713 2

Abstract:

A data processing system ( ) is configured when coming out of reset using memories of various bit widths ( ). The bytes that make up the reset vector ( ) are fetched individually through separate memory operations from the memory that stores the reset vector. These bytes are stored in a pre-determined manner within each of the potential memory structures ( ) such that predetermined addresses will retrieve the different bytes on the same portion of the data bus. A configuration value ( ) portion of the reset vector ( ) retrieved may be used to configure various parameters ( ) within the data processing system ( ) such that parameters related to the memory or other functional characteristics of the system are initialized. The configuration value ( ) may include data and control sections such that the control section determines how the data section of the configuration value ( ) is applied to various parameters within the data processing system ( ).

US Patent:

6769076, Jul 27, 2004

Filed:

Feb 7, 2000

Appl. No.:

09/498812

Inventors:

William C. Moyer - Dripping Springs TX
Michael D. Fitzsimmons - Austin TX
Richard G. Collins - Austin TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1100

US Classification:

714 30, 714 37

Abstract:

A real-time processor debug system that selectively samples address and data signals of a virtual bus of a core processor during real-time operations to reduce power consumption and to minimize performance impact due to bus loading. Gating logic for an embedded processor provides the virtual bus signals of a core processor, including address and data signals, to a debug interface of an embedded system chip or integrated circuit (IC). The gating logic receives update data and update address signals from the debug interface to control switching on corresponding debug address and data buses. The core processor provides processor status signals to the debug interface so that the debug interface determines the particular transaction being performed by the core processor. The processor status signals indicate change of flow (COF) events as well as instruction fetch or data fetch cycles.

US Patent:

6954821, Oct 11, 2005

Filed:

Jul 31, 2003

Appl. No.:

10/631167

Inventors:

Michael D. Fitzsimmons - Austin TX, US
William C. Moyer - Dripping Springs TX, US
Brett W. Murdock - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F013/00

US Classification:

710317, 710240

Abstract:

A crossbar switch () arbitrates for access from multiple bus masters (and ) to multiple addressed slave ports (and ) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch () uses shared slave port control circuitry (), configuration registers () and slave port arbiter logic (and ) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

US Patent:

7099973, Aug 29, 2006

Filed:

Mar 26, 2003

Appl. No.:

10/402165

Inventors:

William C. Moyer - Dripping Springs TX, US
Michael D. Fitzsimmons - Austin TX, US
Brett W. Murdock - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/36
G06F 3/00

US Classification:

710118, 710 18, 710110, 710116

Abstract:

A system () having a plurality of bus masters () coupled to an arbiter () is disclosed. An arbiter () is coupled to a first storage location () and a second storage location (), where the first and second storage locations store bus master parking information for a system bus (). The arbiter () receives a parking context indicator () that is used to select one of the first and second storage locations () to provide bus master parking information to the arbiter ().

US Patent:

7155618, Dec 26, 2006

Filed:

Mar 8, 2002

Appl. No.:

10/094053

Inventors:

William C. Moyer - Dripping Springs TX, US
Brian M. Millar - Austin TX, US
Michael D. Fitzsimmons - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1/32
G06F 1/26

US Classification:

713320, 713322

Abstract:

Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.

US Patent:

7185121, Feb 27, 2007

Filed:

Aug 15, 2005

Appl. No.:

11/203935

Inventors:

Michael D. Fitzsimmons - Austin TX, US
William C. Moyer - Dripping Springs TX, US
Brett W. Murdock - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/28

US Classification:

710 26, 710244, 710317

Abstract:

A crossbar switch () arbitrates for access from multiple bus masters ( and ) to multiple addressed slave ports ( and ) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch () uses shared slave port control circuitry (), configuration registers () and slave port arbiter logic ( and ) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

US Patent:

7185249, Feb 27, 2007

Filed:

Apr 30, 2002

Appl. No.:

10/135877

Inventors:

Thomas Tkacik - Phoeniz AZ, US
Jonathan Lutz - Kitchener, CA
Lawrence Case - Phoenix AZ, US
Douglas Hardy - Scottsdale AZ, US
Mark Redman - Gilbert AZ, US
Gregory Schmidt - Chandler AZ, US
Michael D. Fitzsimmons - Austin TX, US
Darrell L. Carder - Dripping Springs TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/28
H03K 19/00

US Classification:

714726, 326 16

Abstract:

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

US Patent:

7266848, Sep 4, 2007

Filed:

Mar 18, 2002

Appl. No.:

10/100462

Inventors:

William C. Moyer - Dripping Springs TX, US
Michael D. Fitzsimmons - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 21/00

US Classification:

726 29, 713194

Abstract:

The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC () against unauthorized accesses. In one embodiment, an identifier is provided external to IC. A corresponding input IC security key () is then provided to IC and compared to a stored IC security key (). If the input IC security key () and the stored IC security key () do not match, access to protected functional circuitry () is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149. 1 interface defined by the IEEE.