Michael Hamilton

US Patent:

20190233637, Aug 1, 2019

Filed:

Jun 26, 2017

Appl. No.:

16/311237

Inventors:

- Frankfurt am Main, DE
Michael HAMILTON - Brownstown MI, US
Michiel VERSWYVEL - Brussels, BE
Eike JAHNKE - Aubonne, CH
Bernd ELBERT - Harsefeld, DE
Norbert NIESSNER - Friedelsheim, DE
Konrad KNOLL - Mannheim, DE

International Classification:

C08L 53/02
C08J 5/18
C08J 3/20

Abstract:

The present invention relates to a polymer composition comprising at least one block copolymer and a specific amount of at least one oil component. The block copolymer, which is the polymeric matrix of the inventive composition, is built up from at least one vinyl aromatic monomer Mand at least one conjugated diene monomer M, in particular the block copolymer is a styrene butadiene block copolymer (SBC).

US Patent:

20160297961, Oct 13, 2016

Filed:

Nov 11, 2014

Appl. No.:

15/035692

Inventors:

- Frankfurt, DE
Michael HAMILTON - Brownstown MI, US

International Classification:

C08L 67/04
C08F 297/04

Abstract:

The present invention relates to a polymer blend comprising 75-99.5% (w/w) of at least one polylactic acid) (PLA) and 0.5-25% (w/w) of at least one styrene butadiene copolymer containing at least 50% (w/w) styrene. The present invention further relates to the use of such polymer blend for producing products and to the resulting products. Moreover, an object of the present invention is the use of a styrene butadiene block copolymer having a dendrimer structure comprising 50-85% (w/w) styrene as an additive of polymer blends comprising at least 50% (w/w) of PLA and a method of producing the polymer blend according to the invention.

US Patent:

20150346279, Dec 3, 2015

Filed:

Aug 11, 2015

Appl. No.:

14/823338

Inventors:

- Armonk NY, US
Ryan A. Fitch - Southfield MI, US
Michael J. Hamilton - Rochester MN, US
Amanda R. Kaufer - Rochester MN, US

International Classification:

G01R 31/3177

Abstract:

An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.

US Patent:

20150039957, Feb 5, 2015

Filed:

Jul 31, 2013

Appl. No.:

13/955619

Inventors:

- Armonk NY, US
Ryan A. Fitch - Southfield MI, US
Michael J. Hamilton - Rochester MN, US
Amanda R. Kaufer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/27

US Classification:

714733

Abstract:

A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.

US Patent:

20140331097, Nov 6, 2014

Filed:

May 6, 2013

Appl. No.:

13/887674

Inventors:

- Armonk NY, US
Ryan A. Fitch - Southfield MI, US
Michael J. Hamilton - Rochester MN, US
Amanda R. Kaufer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/3177

US Classification:

714727

Abstract:

An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.

US Patent:

20140325298, Oct 30, 2014

Filed:

Jul 11, 2014

Appl. No.:

14/328788

Inventors:

- Armonk NY, US
Ryan A. Fitch - Southfield MI, US
Michael J. Hamilton - Rochester MN, US
Amanda R. Kaufer - Rochester MN, US

International Classification:

G01R 31/3177

US Classification:

714726

Abstract:

A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.

US Patent:

20140201575, Jul 17, 2014

Filed:

Jan 11, 2013

Appl. No.:

13/739727

Inventors:

- Armonk NY, US
Ryan A. Fitch - Southfield MI, US
Michael J. Hamilton - Rochester MN, US
Dennis M. Rickert - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 11/273

US Classification:

714 40

Abstract:

Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores.

US Patent:

20140189612, Jul 3, 2014

Filed:

Jan 3, 2013

Appl. No.:

13/733248

Inventors:

- Armonk NY, US
Ryan A. Fitch - Southfield MI, US
Michael J. Hamilton - Rochester MN, US
Amanda R. Kaufer - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 52

Abstract:

A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.