Michael Wayne Hauser

US Patent:

7550730, Jun 23, 2009

Filed:

Apr 8, 2008

Appl. No.:

12/099304

Inventors:

Ethan H. Cannon - Essex Junction VT, US
Michael J. Hauser - Bolton VT, US
Timothy D. Sullivan - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01T 1/178

US Classification:

25037002

Abstract:

The invention relates to a method of detecting alpha particles in SOI technology and a circuit thereof. The structure is a silicon-on-insulator radiation detector which includes: a charge collection node; a precharge transistor that has a source from the charge collection node, a drain at Vdd, and a gate controlled by a precharge signal; an access transistor that has a source from the charge collection node, a drain connecting to a readout node, and a gate controlled by a read-out signal; and a detector pulldown transistor having a drain from the charge collection node, a source to ground, and a grounded gate.

US Patent:

7659497, Feb 9, 2010

Filed:

Dec 6, 2005

Appl. No.:

11/275058

Inventors:

Wagdi W. Abadeer - Jericho VT, US
James W. Adkisson - Jericho VT, US
Jeffrey S. Brown - Middlesex VT, US
Kiran V. Chatty - Williston VT, US
Michael J. Hauser - Bolton VT, US
Jed H. Rankin - South Burlington VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01J 1/44
H01L 23/62

US Classification:

250206, 250214 R, 257356

Abstract:

Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i. e. , replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.

US Patent:

7875854, Jan 25, 2011

Filed:

Apr 8, 2008

Appl. No.:

12/099307

Inventors:

Ethan H. Cannon - Essex Junction VT, US
Michael J. Hauser - Bolton VT, US
Timothy D. Sullivan - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01T 1/178

US Classification:

25037002

Abstract:

The invention relates to a design structure, and more particularly, to a design structure for an alpha particle sensor in SOI technology and a circuit thereof. The structure is a silicon-on-insulator radiation detector which includes: a charge collection node; a precharge transistor that has a source from the charge collection node, a drain at Vdd, and a gate controlled by a precharge signal; an access transistor that has a source from the charge collection node, a drain connecting to a readout node, and a gate controlled by a read-out signal; and a detector pulldown transistor having a drain from the charge collection node, a source to ground, and a grounded gate.

US Patent:

7915571, Mar 29, 2011

Filed:

Dec 23, 2009

Appl. No.:

12/646292

Inventors:

Wagdi W. Abadeer - Jericho VT, US
James W. Adkisson - Jericho VT, US
Jeffrey S. Brown - Middlesex VT, US
Kiran V. Chatty - Williston VT, US
Michael J. Hauser - Bolton VT, US
Jed H. Rankin - South Burlington VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01J 40/14
H03K 17/78
H02H 9/00
G01R 27/26

US Classification:

250206, 250214 R, 250214 SW, 361 56, 324662

Abstract:

Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i. e. , replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.

US Patent:

8120131, Feb 21, 2012

Filed:

Aug 26, 2009

Appl. No.:

12/547519

Inventors:

Ethan H. Cannon - Essex Junction VT, US
Michael J. Hauser - Bolton VT, US
Timothy D. Sullivan - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31/02

US Classification:

257444, 257443

Abstract:

An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e. g. , a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e. g. , to within 10 s of microns).

US Patent:

8647909, Feb 11, 2014

Filed:

Jan 25, 2012

Appl. No.:

13/357728

Inventors:

Ethan H. Cannon - Essex Junction VT, US
Michael J. Hauser - Bolton VT, US
Timothy D. Sullivan - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438 56, 257E31002

Abstract:

An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e. g. , a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e. g. , to within 10 s of microns).

US Patent:

20150014771, Jan 15, 2015

Filed:

Jul 11, 2013

Appl. No.:

13/939353

Inventors:

- Armonk NY, US
John J. Ellis-Monaghan - Grand Isle VT, US
Michael J. Hauser - Bolton VT, US
Jeffrey B. Johnson - Essex Junction VT, US
Xuefeng Liu - South Burlington VT, US

International Classification:

H01L 29/78
H01L 29/66

US Classification:

257343, 438294

Abstract:

A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does.

US Patent:

20140339607, Nov 20, 2014

Filed:

Aug 5, 2014

Appl. No.:

14/451836

Inventors:

- Armonk NY, US
Michael J. Hauser - Bolton VT, US
Zhong-Xiang He - Essex Junction VT, US
Junjun Li - Williston VT, US
Xuefeng Liu - South Burlington VT, US
Anthony K. Stamper - Williston VT, US

International Classification:

B81C 1/00

US Classification:

257254

Abstract:

A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.