Michael Robert Knowles

US Patent:

6487628, Nov 26, 2002

Filed:

Mar 31, 1999

Appl. No.:

09/283773

Inventors:

Peter H. Duong - Santa Clara CA
Michael W. Knowles - Santa Clara CA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1342

US Classification:

710313, 710305

Abstract:

A peripheral control interface provides access to a system area network for a plurality of peripheral devices connected to the PCI through an I/O bus. A plurality of virtual data channels is defined in local memory to which outstanding requests from peripherals are assigned. Physical channel engines implement the order requests through the assigned virtual data channel with accessed data stored in local memory. A subsequent request by a peripheral can then be immediately fulfilled from data stored in memory. Data channel context stored in memory includes the number of outstanding requests by a user to whom the channel is dedicated, and a physical channel engine can pre-fetch data in response to a plurality of outstanding requests from a peripheral thereby eliminating latency in fulfilling requests.

US Patent:

6754737, Jun 22, 2004

Filed:

Dec 24, 2001

Appl. No.:

10/035983

Inventors:

Tom A. Heynemann - Boulder Creek CA
Jeffrey A. Sprouse - Mountain View CA
Michael W. Knowles - Santa Clara CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 300

US Classification:

710 39, 710112

Abstract:

A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

US Patent:

7308522, Dec 11, 2007

Filed:

Jun 9, 2004

Appl. No.:

10/864617

Inventors:

Tom A. Heynemann - Boulder Creek CA, US
Jeffrey A. Sprouse - Mountain View CA, US
Michael W. Knowles - Santa Clara CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36

US Classification:

710310, 710311, 710306

Abstract:

A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

US Patent:

7890706, Feb 15, 2011

Filed:

Nov 16, 2004

Appl. No.:

10/990151

Inventors:

David J. Garcia - Los Gatos CA, US
Michael Knowles - Santa Clara CA, US
Tom A. Heynemann - Boulder Creek CA, US
Jeffrey A. Sprouse - Mountain View CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/14

US Classification:

711150, 711141, 710244, 714 12, 714797

Abstract:

In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.

US Patent:

20030131175, Jul 10, 2003

Filed:

Dec 24, 2001

Appl. No.:

10/035988

Inventors:

Tom Heynemann - Boulder Creek CA, US
Jeffrey Sprouse - Mountain View CA, US
Michael Knowles - Santa Clara CA, US

International Classification:

G06F013/36

US Classification:

710/310000

Abstract:

A method and apparatus of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions, on which the read transaction request depends, pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

US Patent:

20080065799, Mar 13, 2008

Filed:

Nov 9, 2007

Appl. No.:

11/938116

Inventors:

Tom Heynemann - Boulder Creek CA, US
Jeffrey Sprouse - Mountain View CA, US
Michael Knowles - Santa Clara CA, US

International Classification:

G06F 13/14

US Classification:

710110000

Abstract:

A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.