Michael J Weber

US Patent:

20120028505, Feb 2, 2012

Filed:

Jul 17, 2011

Appl. No.:

13/184552

Inventors:

Michael Weber - Collegeville PA, US
Eric Burkett - Hillsborough NJ, US
Brian Zigmond - Newark DE, US

International Classification:

H01R 33/92

US Classification:

439638

Abstract:

The present invention disclosed relates to a flexible electrical outlet strip that is comprised of a series of electric receptacles joined by independent ball and socket modules. Each ball and socket module is electrically interconnected with the power source and capable of rotating 360 degrees while maintaining electrical continuity. Each ball and socket connection also provides up to 60 degrees of pivotal movement at each socket joint. A fixed single-axis pivotal hinge joins receptacles to increasing mobility and possible outlet configurations. Combined, these characteristics will enable each electric receptacle to be positioned in a unique configuration to accommodate bulky and odd-shaped plugs and power adapters, conform into flexible shapes and designs for space constrained areas, hang or wrap around objects, and assist with cord management.

US Patent:

61051543, Aug 15, 2000

Filed:

May 29, 1998

Appl. No.:

9/087837

Inventors:

Andrew A. Wang - Wescosville PA
Michael J. Weber - Wescosville PA

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

G06F 11277
G06F 1314
H04B 1700

US Classification:

714732

Abstract:

A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a plurality of buses, each of the buses having multiple data lines for transferring data based on the data transfer protocols, a multiplexer coupled to the plurality of buses for multiplexing the data onto parallel lines and a CRC signature compactor coupled to the parallel lines for receiving the data. The CRC signature compactor compresses the data and (1) provides a fault-free signature representative of the data in a known fault-free chip, and (2) provides another signature representative of the data in a chip under test, wherein the two signatures are compared to determine whether a fault exists in the chip under test.