Ming Chieh Huang

US Patent:

7657767, Feb 2, 2010

Filed:

Jun 30, 2005

Appl. No.:

11/174204

Inventors:

Stefan Rusu - Sunnyvale CA, US
Kevin Zhang - Portland CA, US
Fatih Hamzaoglu - Hillsboro OR, US
Jonathan Shoemaker - Sunnyvale CA, US
Ming Huang - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00
G06F 1/32

US Classification:

713323, 713300, 713320, 713330, 326 33, 326 34, 326 83

Abstract:

In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

US Patent:

7848166, Dec 7, 2010

Filed:

Mar 11, 2008

Appl. No.:

12/046276

Inventors:

Kuoyuan Peter Hsu - San Jose CA, US
Young Suk Kim - San Jose CA, US
Bing Wang - Milpitas CA, US
Ming Chieh Huang - San Jose CA, US

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu

International Classification:

G11C 7/08
G11C 7/12

US Classification:

365203, 365204, 365205

Abstract:

A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.

US Patent:

20060146810, Jul 6, 2006

Filed:

Dec 30, 2004

Appl. No.:

11/024430

Inventors:

Thanh Bui - Fremont CA, US
Ming Huang - Marlboro NJ, US
Vikram Meghal - Bangalore, IN
Alvin Topol - Mountain View CA, US

International Classification:

H04L 12/28

US Classification:

370386000, 370465000

Abstract:

The multiple subscriber port architecture includes a first shelf having at least one port, and a controller controlling operation of the first shelf. At least one second shelf has at least one interface connected to one of the ports of the first shelf. The second shelf also has a number of ports. The controller of the first shelf is configured to control operation of the second shelf.

US Patent:

20160254431, Sep 1, 2016

Filed:

May 5, 2016

Appl. No.:

15/147850

Inventors:

- Fremont CA, US
Chung Chi Chang - San Jose CA, US
Ming Chieh Huang - Fremont CA, US

International Classification:

H01L 33/62
H01L 33/58
H01L 33/48
H01L 23/498
H01L 21/48
H01L 33/64

Abstract:

A method is provided for manufacturing a LED package base including providing a metal core substrate having a top surface and a bottom surface and forming two first trenches in the metal core substrate. The first trenches extend from the top surface to the bottom surface. The method further includes at least partially filling in the first trenches with first dielectric material to form dielectric isolations. The dielectric isolations divide the metal core substrate into three metal core portions. Two of the metal core portions may be configured to serve as LED package electrodes. The method also includes applying a second dielectric material to cover at least a portion of the first dielectric material, and forming a conductive layer over the second dielectric material to form circuit contacts. The conductive layer includes a first conductive material.

US Patent:

20140372923, Dec 18, 2014

Filed:

Jun 14, 2013

Appl. No.:

13/918645

Inventors:

- Redmond WA, US
John Wesley Terrell - Kirkland WA, US
Fei Xiong - Redmond WA, US
Michael J. Ens - Redmond WA, US
Xiao Tu - Medina WA, US
Nicolas J. Brun - Seattle WA, US
Ming Huang - Bellevue WA, US
Jan-Kristian Markiewicz - Redmond WA, US
Alan William Stephenson - Redmond WA, US
Michael John Patten - Sammamish WA, US
Jon Gabriel Clapper - Seattle WA, US

International Classification:

G06F 3/0486
G06F 3/0488

US Classification:

715769

Abstract:

High performance touch drag and drop are described. In embodiments, a multi-threaded architecture is implemented to include at least a manipulation thread and an independent hit test thread. The manipulation thread is configured to receive one or more messages associated with an input and send data associated with the messages to the independent hit test thread. The independent hit test thread is configured to perform an independent hit test to determine whether the input hit an element that is eligible for a particular action, and identify an interaction model associated with the input. The independent hit test thread also sends an indication of the interaction model to the manipulation thread to enable the manipulation thread to detect whether the particular action is triggered.