Mohammad F Ahmad

US Patent:

20090201989, Aug 13, 2009

Filed:

Oct 31, 2008

Appl. No.:

12/263129

Inventors:

Sherjil Ahmed - Irvine CA, US
Mohammed Usman - Mission Viejo CA, US
Mohammad Ahmad - Irvine CA, US

International Classification:

H04N 7/12
H04N 7/26

US Classification:

37524008, 37524025, 375E07027, 375E07026

Abstract:

The present invention provides for an improved video compression and encoding that optimizes and enhances the overall speed and efficiency of processing video data. In one embodiment, the video codec transmits the output of an entropy decoder to a lossless compressor and memory before going through inverse discrete cosine transformation and motion compensation blocks.

US Patent:

20090328048, Dec 31, 2009

Filed:

Dec 16, 2008

Appl. No.:

12/335644

Inventors:

Shoab Ahmad Khan - Islamabad, PK
M. Mohsin Rehmatullah - Islamabad, PK
Sherjil Ahmed - Irvine CA, US
Mohammed Usman - Mission Viejo CA, US
Mohammad Ahmad - Irvine CA, US

Assignee:

Quartics, Inc. - Irvine CA

International Classification:

G06F 9/46

US Classification:

718102

Abstract:

The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks. The hardware system architecture of the said novel gateway is comprised of a plurality of DPLPs, referred to as Media Engines that are interconnected with a Host Processor or Packet Engine, which, in turn, is in communication with interfaces to networks. Each of the PUs within the processing layers of the Media Engines are specially designed to perform a class of media processing specific tasks, such as line echo cancellation, encoding or decoding data, or tone signaling.

US Patent:

20100321579, Dec 23, 2010

Filed:

Feb 11, 2010

Appl. No.:

12/704472

Inventors:

Mohammad Ahmad - Tustin CA, US
Mohammad Usman - Mission Viejo CA, US
Sherjil Ahmed - Irvine CA, US

International Classification:

H04N 5/21
G06F 15/76
G06F 9/02
H04N 7/30
H04N 5/14

US Classification:

348607, 712 37, 3752402, 348699, 712E09002, 375E07226, 348E05062, 348E05077

Abstract:

The present specification discloses a processing architecture that has multiple levels of parallelism and is highly configurable, yet optimized for media processing. At the highest level, the architecture is structured to enable each processor, which is dedicated to a specific media processing function, to operate substantially in parallel. In addition to processor-level parallelism, each processing unit can operate on multiple words in parallel, rather than just a single word per clock cycle. Moreover, at the instruction level, the control data memory, data memory, and function specific dath paths can be controlled all within the same clock cycle. Additionally, the processor has multiple layers of configurability, with the extendable data path of the processor being capable of being configured to perform specific processing functions, such as entropy encoding, discrete cosine transform (DCT), inverse discrete cosine transform (IDCT), motion compensation, motion estimation, de-blocking filter, de-interlacing, de-noising, quantization, and dequantization.