Muhammad A Ahmed

US Patent:

6704772, Mar 9, 2004

Filed:

Sep 20, 1999

Appl. No.:

09/399417

Inventors:

Muhammad A. Ahmed - Seattle WA
Mohammad Shabbir Alam - Bellevue WA

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 1516

US Classification:

709207, 709206

Abstract:

Systems and methods for providing electronic messaging services to multiple users by storing a single copy of an electronic message at a central location and notifying recipients of the stored single copy. An electronic message includes a distribution list and a message content. A distribution list identifying multiple recipients causes prior art systems to duplicate the entire message for each recipient, placing potentially large demands on both processing power and storage space. In contrast, the systems and methods disclosed herein store a single copy or a limited number of copies of an electronic message addressed to multiple recipients and provide each recipient with a relatively small notification. In addition to providing information regarding content and origin, the notification also provides access to the stored message. Furthermore, the methods and systems also aid in organizing replies to electronic messages.

US Patent:

7328251, Feb 5, 2008

Filed:

Jan 8, 2004

Appl. No.:

10/753705

Inventors:

Muhammad A. Ahmed - Redmond WA, US
Mohammad Shabbir Alam - Redmond WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 15/16

US Classification:

709207, 709204

Abstract:

Systems and methods for providing electronic messaging services to multiple users by storing a single copy of an electronic message at a central location and notifying recipients of the stored single copy. An electronic message includes a distribution list and a message content. A distribution list identifying multiple recipients causes prior art systems to duplicate the entire message for each recipient, placing potentially large demands on both processing power and storage space. In contrast, the systems and methods disclosed herein store a single copy or a limited number of copies of an electronic message addressed to multiple recipients and provide each recipient with a relatively small notification. In addition to providing information regarding content and origin, the notification also provides access to the stored message. Furthermore, the methods and systems also aid in organizing replies to electronic messages.

US Patent:

20220318093, Oct 6, 2022

Filed:

Apr 2, 2021

Appl. No.:

17/221751

Inventors:

- Redmond WA, US
Muhammad Ashfaq AHMED - Redmond WA, US
Tom Long NGUYEN - Auburn WA, US
Neeraj LADKANI - Bothell WA, US

International Classification:

G06F 11/14
G06F 11/07

Abstract:

To preserve error context during a reboot of a computing device, firmware within the computing device can be configured to implement a method that includes determining where the error context is stored in volatile memory. The method can also include identifying a plurality of recorder regions in non-volatile memory that have been assigned to store the error context. The plurality of recorder regions can be disaggregated across a plurality of distinct non-volatile memory regions. The method can also include flushing the error context from a plurality of different volatile memory locations to the plurality of recorder regions in response to detecting a trigger. The flushing can occur prior to the reboot of the computing device. The method can also include restoring at least some of the error context to the volatile memory after the computing device has been rebooted.

US Patent:

20230067317, Mar 2, 2023

Filed:

Oct 24, 2022

Appl. No.:

18/049086

Inventors:

- Redmond WA, US
Muhammad A. AHMED - Redmond WA, US
Bryan D. KELLY - Carnation WA, US
Ramakoti R. BHIMANADHUNI - Bothell WA, US
Pingfan SONG - Newcastle WA, US

Assignee:

Microsoft Technology Licensing, LLC - Redmond WA

International Classification:

G06F 8/65
G06F 9/46
G06F 9/455
G06F 9/445
G06F 9/48

Abstract:

A computing device is provided, including memory storing an instruction storage location. The computing device may further include a processor system including a plurality of processor threads. The processor system may suspend execution of one or more respective processor threads of the plurality of processor threads. The processor system may store one or more respective processor thread contexts of the one or more processor threads in the memory. The processor system may enter a system management mode (SMM). The processor system may determine that the instruction storage location includes a code update instruction. The processor system may perform a code update based on the code update instruction. The processor system may exit the SMM. The processor system may retrieve the one or more processor thread contexts from the memory and resume execution of the one or more processor threads without rebooting the computing device.

US Patent:

20230055136, Feb 23, 2023

Filed:

Aug 19, 2021

Appl. No.:

17/406961

Inventors:

- Redmond WA, US
Mallik BULUSU - Bellevue WA, US
Tom Long NGUYEN - Auburn WA, US
Muhammad Ashfaq AHMED - Redmond WA, US
Madhav Himanshubhai PANDYA - Redmond WA, US

International Classification:

G06F 12/0804
G06F 13/40

Abstract:

A computing system that enables data stored in a persistent memory region to be preserved when a processor fails can include volatile memory comprising the persistent memory region, non-volatile memory, and a system on a chip (SoC). The SoC can include a main processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include an auxiliary processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.

US Patent:

20210311833, Oct 7, 2021

Filed:

Apr 1, 2020

Appl. No.:

16/837885

Inventors:

- Redmond WA, US
Tom Long NGUYEN - Auburn WA, US
Muhammad Ashfaq AHMED - Redmond WA, US

International Classification:

G06F 11/14
G06F 11/20
G06F 11/16
G06F 11/07
G06F 11/30
G06F 21/57
G06F 21/73

Abstract:

A method for targeted repair of a hardware component in a computing device that is part of a cloud computing system includes monitoring a plurality of hardware components in the computing device. At some point, a defective sub-component within the hardware component of the computing device is identified. In addition to the defective sub-component, the hardware component also includes at least one sub-component that is functioning properly and a spare component that can be used in place of the defective sub-component. The method also includes initiating a targeted repair action while the computing device is connected to the cloud computing system. The targeted repair action prevents the defective sub-component from being used by the computing device without preventing sub-components that are functioning properly from being used by the computing device. The targeted repair action causes the spare component to be used in place of the defective sub-component.

US Patent:

20210294763, Sep 23, 2021

Filed:

Mar 18, 2020

Appl. No.:

16/823316

Inventors:

- Redmond WA, US
Mallik BULUSU - Bellevue WA, US
Sagar DHARIA - Bellevue WA, US
Muhammad Ashfaq AHMED - Redmond WA, US

International Classification:

G06F 13/24
G06F 9/4401
G06F 9/30
G06F 11/30
G06F 9/54

Abstract:

A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.

US Patent:

20210240489, Aug 5, 2021

Filed:

May 14, 2020

Appl. No.:

16/874276

Inventors:

- Redmond WA, US
Thirupathaiah ANNAPUREDDY - Redmond WA, US
Mallik BULUSU - Bellevue WA, US
Muhammad Ashfaq AHMED - Redmond WA, US

Assignee:

Microsoft Technology Licensing, LLC - Redmond WA

International Classification:

G06F 9/4401
G06F 9/54
G06F 8/654
G06F 21/64
G06F 21/57

Abstract:

A computing system is provided, including a processor and memory storing instructions that, when executed, cause the processor to store a firmware update patch in a runtime buffer included in the memory. The runtime buffer may be accessible by firmware and an operating system of the computing system. The processor may perform a first verification check on the firmware update patch. When the firmware update patch passes the first verification check, the processor may copy the firmware update patch to a system management random access memory (SMRAM) buffer included in the memory. The SMRAM buffer may be accessible by the firmware and inaccessible by the operating system. The processor may perform a second verification check on the copy of the firmware update patch. When the copy of the firmware update patch passes the second verification check, the processor may execute the copy of the firmware update patch.