Muhammad A Ahmed

US Patent:

7383420, Jun 3, 2008

Filed:

Mar 24, 2005

Appl. No.:

11/089619

Inventors:

Erich Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
Muhammad Ahmed - Austin TX, US
William C. Anderson - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/26
G06F 9/34

US Classification:

711220, 712 E904

Abstract:

A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.

US Patent:

7523295, Apr 21, 2009

Filed:

Mar 21, 2005

Appl. No.:

11/086475

Inventors:

Lucian Codrescu - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
Sujat Jamil - Austin TX, US
William C. Anderson - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/30
G06F 9/40

US Classification:

712214, 712216, 712218

Abstract:

An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.

US Patent:

7526633, Apr 28, 2009

Filed:

Mar 23, 2005

Appl. No.:

11/088607

Inventors:

Lucian Codrescu - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
William C. Anderson - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/30
G06F 15/00

US Classification:

712210, 712209

Abstract:

Techniques for processing transmissions in a communications (e. g. , CDMA) system. The method and system encode and process instructions of mixed lengths (e. g. , 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.

US Patent:

7584326, Sep 1, 2009

Filed:

Sep 12, 2006

Appl. No.:

11/531111

Inventors:

Muhammad Ahmed - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 12/12

US Classification:

711128, 711133, 711136

Abstract:

Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag miss allocation. Herein, steps and instructions provide for forming a first-in, first-out (FIFO) cache way listing of victim ways for the cache memory, wherein the depth of the FIFO cache way listing approximately equals the number of ways in the cache memory. The method and system place a victim way on the FIFO cache way listing only in the event that a tag miss results in a tag miss allocation, the victim way is placed at the tail of the FIFO cache way listing after any previously selected victim way. Use of a victim way on the FIFO cache way listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.

US Patent:

7590824, Sep 15, 2009

Filed:

Mar 29, 2005

Appl. No.:

11/093375

Inventors:

Muhammad Ahmed - Austin TX, US
Erich Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/30

US Classification:

712214, 712 23, 712 24

Abstract:

Techniques for processing transmissions in a communications (e. g. , CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e. g. , VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e. g. , superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.

US Patent:

7620778, Nov 17, 2009

Filed:

May 25, 2005

Appl. No.:

11/137183

Inventors:

Baker Mohammad - Austin TX, US
Muhammad Ahmed - Austin TX, US
Paul Bassett - Austin TX, US
Sujat Jamil - Austin TX, US
Ajay Anant Ingle - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 12/00

US Classification:

711144, 711154, 711156

Abstract:

Techniques for processing transmissions in a communications (e. g. , CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines.

US Patent:

7673102, Mar 2, 2010

Filed:

May 17, 2006

Appl. No.:

11/437501

Inventors:

Muhammad Ahmed - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 12/00

US Classification:

711128, 711133, 711136

Abstract:

Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag-miss allocation. Herein, steps forming a first-in, first-out (FIFO) replacement listing of victim ways for the cache memory, wherein the depth of the FIFO replacement listing approximately equals the number of ways in the cache set. The method and system place a victim way on the FIFO replacement listing only in the event that a tag-miss results in a tag-miss allocation, the victim way is placed at the tail of the FIFO replacement listing after any previously selected victim way. Use of a victim way on the FIFO replacement listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.

US Patent:

7685411, Mar 23, 2010

Filed:

Apr 11, 2005

Appl. No.:

11/104115

Inventors:

Muhammad Ahmed - Austin TX, US
Lucian Codrescu - Austin TX, US
Erich Plondke - Austin TX, US
William C. Anderson - Austin TX, US
Robert Allan Lester - Round Rock TX, US
Phillip M. Jones - Round Rock TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/00

US Classification:

712241, 712239

Abstract:

An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

Address:

4712 Hibiscus Vly Dr, Austin, TX 78739

Phone:

(512)2801182

VIN:

1GYFK63837R147969

Make:

CADI

Model:

ESCA

Year:

2007