Muhammad N Ahmed

US Patent:

20100281234, Nov 4, 2010

Filed:

Apr 30, 2009

Appl. No.:

12/433826

Inventors:

MUHAMMAD AHMED - Hayward CA, US
Marc Schaub - Sunnyvale CA, US
Shlomo Selim Rakib - Cupertino CA, US

Assignee:

Novafora, Inc. - San Jose CA

International Classification:

G06F 9/30
G06F 15/80
G06F 9/02

US Classification:

712 2, 712220, 712 10, 712E09016, 712E09002

Abstract:

A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of registers in the processor to store second data and second instructions associated with a second thread. The method may further include transmitting the first data and first instructions associated with the first thread to the first set of registers, and executing the first instructions in order to process the first data. The method may further include transmitting the second data and second instructions to the second set of registers while executing the first instructions and processing the first data. A corresponding apparatus is also disclosed and claimed herein.

US Patent:

20100281236, Nov 4, 2010

Filed:

Apr 30, 2009

Appl. No.:

12/433821

Inventors:

Shlomo Selim Rakib - Cupertino CA, US
Muhammad Ahmed - Hayward CA, US
Marc Schaub - Sunnyvale CA, US

Assignee:

Novafora, Inc. - San Jose CA

International Classification:

G06F 9/30
G06F 15/80
G06F 9/06

US Classification:

712 17, 712225, 712228, 712E09016, 712E09003

Abstract:

An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly to at least one neighboring processing element within the array. In selected embodiments, the apparatus may include exchange registers to temporarily store data transferred between neighboring processing elements.

US Patent:

20100281483, Nov 4, 2010

Filed:

Apr 30, 2009

Appl. No.:

12/433824

Inventors:

Shlomo Selim Rakib - Cupertino CA, US
Alexander Hubris - San Jose CA, US
Muhammad Ahmed - Hayward CA, US

Assignee:

Novafora, Inc. - San Jose CA

International Classification:

G06F 9/46
G06F 12/00

US Classification:

718102, 711108, 712 30

Abstract:

A scheduling co-processor for scheduling the execution of threads on a processor is disclosed. In certain embodiments, the scheduling co-processor includes one or more engines (such as lookup tables) that are programmable with a Petri-net representation of a thread scheduling algorithm. The scheduling co-processor may further include a token list to store tokens associated with the Petri-net; an enabled-thread list to indicate which threads are enabled for execution in response to particular tokens being present in the token list; and a ready-thread list to indicate which threads from the enabled-thread list are ready for execution when data and/or space availability conditions associated with the threads are satisfied.