Muhammad S Hussain

US Patent:

7240203, Jul 3, 2007

Filed:

Dec 19, 2001

Appl. No.:

10/025509

Inventors:

Richard E. Kessler - Shrewsbury MA, US
David A. Carlson - Haslet TX, US
Muhammad Raghib Hussain - Pleasanton CA, US
Robert A. Sanzone - Hudson MA, US
Khaja E. Ahmed - Pleasanton CA, US
Michael D. Varga - Milpitas CA, US

Assignee:

Cavium Networks, Inc. - Mountain View CA

International Classification:

H04L 9/00

US Classification:

713171

Abstract:

A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.

US Patent:

7398386, Jul 8, 2008

Filed:

Apr 12, 2003

Appl. No.:

10/411909

Inventors:

Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium Networks, Inc. - Mountain View CA

International Classification:

G06F 21/00
G06F 15/16
H04L 9/00
H04K 1/00

US Classification:

713150, 726 14

Abstract:

A method and apparatus for transparent processing of IPsec network traffic by a security processor in line between a framer and a network processor. Security processor parses packet header and tail information to determine if encryption or decryption is required. After encryption or decryption is completed packet header and tail information is modified to reflect the changes in the packet such as length of the packet. The modified packet is then passed on to the network processor or framer.

US Patent:

7602919, Oct 13, 2009

Filed:

Mar 16, 2005

Appl. No.:

11/082068

Inventors:

Audrius Berzanskis - Cambridge MA, US
Harri Hakkarainen - Los Gatos CA, US
Keun Lee - Newburyport MA, US
Muhammad Raghib Hussain - Pleasanton CA, US

Assignee:

MagiQ Technologies, Inc - New York NY

International Classification:

H04L 9/12
H04L 29/06

US Classification:

380277, 380278, 713150

Abstract:

A method of integrating quantum key distribution (QKD) with Internet protocol security (IPSec) to improve the security of IPSec. Standard IPSec protocols impose limits on the frequency at which keys can be changed. This makes efforts to improve the security of IPSec by employing quantum keys problematic. The method includes employing multiple security associations (SA) in in-bound and outbound SA Tables in a manner that enables a high key flipping rate and that enables combining quantum keys with classical keys generated by Internet Key Exchange (IKE), thereby enabling QKD-based IPSec.

US Patent:

20060059286, Mar 16, 2006

Filed:

Jan 25, 2005

Appl. No.:

11/042476

Inventors:

Michael Bertone - Marlborough MA, US
David Carlson - Haslet TX, US
Richard Kessler - Shrewsbury MA, US
Philip Dickinson - Cupertino CA, US
Muhammad Hussain - Pleasanton CA, US
Trent Parker - San Jose CA, US

Assignee:

Cavium Networks - Santa Clara CA

International Classification:

G06F 13/24

US Classification:

710260000

Abstract:

In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.

US Patent:

20130254906, Sep 26, 2013

Filed:

Mar 22, 2012

Appl. No.:

13/427148

Inventors:

Richard E. Kessler - Northborough MA, US
Muhammad Raghib Hussain - Saratoga CA, US
Ethan Frederick Robbins - North Grafton MA, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 21/00

US Classification:

726 34

Abstract:

Authentication and association of hardware and software is accomplished by loading a secure code from an external memory at startup time and authenticating the program code using an authentication key. Access to full hardware and software functionality may be obtained upon authentication of the secure code. However, if the authentication of the secure code fails, an unsecure code that provides limited functionality to hardware and software resources is executed.

US Patent:

6789147, Sep 7, 2004

Filed:

Dec 19, 2001

Appl. No.:

10/025512

Inventors:

Richard E. Kessler - Shrewsbury MA
David A. Carlson - Haslet TX
Muhammad Raghib Hussain - Pleasanton CA
Robert A. Sanzone - Hudson MA
Khaja E. Ahmed - Pleasanton CA
Michael D. Varga - Milpitas CA

Assignee:

Cavium Networks - Santa Clara CA

International Classification:

G06F 900

US Classification:

710200, 713200, 712 34

Abstract:

A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.