Muhammad R Hussain

US Patent:

7594081, Sep 22, 2009

Filed:

Dec 28, 2004

Appl. No.:

11/024002

Inventors:

Gregg A. Bouchard - Round Rock TX, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium Networks, Inc. - Mountain View CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711138

Abstract:

A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

US Patent:

7736954, Jun 15, 2010

Filed:

Aug 28, 2006

Appl. No.:

11/467822

Inventors:

Muhammad Mustafa Hussain - Austin TX, US
Naim Moumen - Walden NY, US
Gabriel Gebara - Austin TX, US
Ed Labelle - Austin TX, US
Sidi Lanee - Austin TX, US
Barry Sassman - Cedar Park TX, US
Raj Jammy - Austin TX, US

Assignee:

Sematech, Inc. - Austin TX

International Classification:

H01L 21/84

US Classification:

438149, 977887, 977888, 257E21561

Abstract:

Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern.

US Patent:

7814310, Oct 12, 2010

Filed:

Apr 12, 2003

Appl. No.:

10/411967

Inventors:

Gregg A. Bouchard - Round Rock TX, US
Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium Networks - Santa Clara CA

International Classification:

H04L 29/06

US Classification:

713153, 713160, 713189, 726 13

Abstract:

A method and apparatus for optimizing IPsec processing by providing execution units with windowing data during prefetch and managing coherency of security association data by management of security association accesses. Providing execution units with windowing data allows initial parallel processing of IPsec packets. The security association access ordering apparatus serializes access to the dynamic section of security association data according to packet order arrival while otherwise allowing parallel processing of the IPsec packet by multiple execution units in a security processor.

US Patent:

8301788, Oct 30, 2012

Filed:

Sep 7, 2005

Appl. No.:

11/220899

Inventors:

Gregg A. Bouchard - Round Rock TX, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 15/16
G06F 15/173
H04L 12/28
H04J 3/06

US Classification:

709230, 709208, 709221, 709231, 709246, 370389, 370392, 370503

Abstract:

A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.

US Patent:

8392590, Mar 5, 2013

Filed:

Sep 7, 2005

Appl. No.:

11/221408

Inventors:

Gregg A. Bouchard - Round Rock TX, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 15/16
G06F 17/28

US Classification:

709230, 704 2

Abstract:

A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.

US Patent:

20070048920, Mar 1, 2007

Filed:

Aug 25, 2005

Appl. No.:

11/212127

Inventors:

Seung-Chul Song - Austin TX, US
Zhibo Zhang - Austin TX, US
Byoung Lee - Austin TX, US
Naim Moumen - Walden NY, US
Joel Barnett - Austin TX, US
Muhammad Hussain - Austin TX, US
Rino Choi - Austin TX, US
Husam Alshareef - Austin TX, US

International Classification:

H01L 21/8238
H01L 21/8234
H01L 21/4763
H01L 21/3205

US Classification:

438199000, 438275000, 438229000, 438592000, 438585000

Abstract:

Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without removing the mask layer, a second metal layer may be deposited. In one embodiment, the mask layer is a second metal layer. In other embodiments, the mask layer is a silicon layer. Subsequent fabrication steps include depositing another metal layer (e.g., another PMOS metal layer), depositing a cap, etching the cap to define gate stacks, and simultaneously etching the first and second gate region having a similar thickness with differing metal layers.

US Patent:

20070059874, Mar 15, 2007

Filed:

Jul 6, 2006

Appl. No.:

11/456054

Inventors:

Naim Moumen - Walden NY, US
Husam Alshareef - Austin TX, US
Joel Barnett - Austin TX, US
Muhammad Hussain - Austin TX, US
Hongfa Luan - Dresden, DE
Seung-Chul Song - Austin TX, US
Raj Jammy - Austin TX, US

International Classification:

H01L 21/8238

US Classification:

438199000, 438296000, 257E21632

Abstract:

Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.

US Patent:

20110006378, Jan 13, 2011

Filed:

Jul 7, 2009

Appl. No.:

12/498775

Inventors:

Muhammad Hussain - Austin TX, US
Chang Seo Park - Austin TX, US

International Classification:

H01L 29/78
H01L 21/3205
H01L 21/311

US Classification:

257392, 438584, 438703, 257E29255, 257E21249, 257E21294

Abstract:

A method of manufacturing a semiconductor device includes depositing a first capping layer on a dielectric layer. The method also includes etching the first capping layer from a second portion of the semiconductor device. The first capping layer remaining in a first portion of the semiconductor device may form a PMOS device. The method further includes depositing a second capping layer after etching the first capping layer. After the second capping layer is deposited a maskless process results in selectively etching the second capping layer from the first portion of the semiconductor device. The second portion of the semiconductor device may be a NMOS device. The method described may be used in manufacturing integrated CMOS devices as scaling reduces device size. Additionally, the method of selectively etching capping layers may be used to manufacture multi-threshold voltage devices.