Peter R Doyle

US Patent:

20220366630, Nov 17, 2022

Filed:

Jul 28, 2022

Appl. No.:

17/876358

Inventors:

- Santa Clara CA, US
ZACK WATERS - Portland OR, US
MICHAEL APODACA - El Dorado Hills CA, US
DANIEL JOHNSTON - Portland OR, US
JASON SURPRISE - Beaverton OR, US
PRASOONKUMAR SURTI - Folsom CA, US
SUBRAMANIAM MAIYURAN - Gold River CA, US
PETER DOYLE - Gold River CA, US
SAURABH SHARMA - El Dorado Hills CA, US
ANKUR SHAH - Folsom CA, US
MURALI RAMADOSS - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 15/00
G06T 15/40
G06T 15/80

Abstract:

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

US Patent:

20220261075, Aug 18, 2022

Filed:

Mar 1, 2022

Appl. No.:

17/683533

Inventors:

- Santa Clara CA, US
Brent E. INSKO - Portland OR, US
Prasoonkumar SURTI - Folsom CA, US
Adam T. LAKE - Portland OR, US
Peter L. DOYLE - El Dorado Hills CA, US
Daniel POHL - Puchheim, DE

International Classification:

G06F 3/01
G02B 27/00

Abstract:

One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

US Patent:

20210272349, Sep 2, 2021

Filed:

May 3, 2021

Appl. No.:

17/306769

Inventors:

- Santa Clara CA, US
ZACK WATERS - Portland OR, US
MICHAEL APODACA - Folsom CA, US
DANIEL JOHNSTON - Portland OR, US
JASON SURPRISE - Beaverton OR, US
PRASOONKUMAR SURTI - Folsom CA, US
SUBRAMANIAM MAIYURAN - Gold River CA, US
PETER DOYLE - El Dorado Hills CA, US
SAURABH SHARMA - El Dorado Hills CA, US
ANKUR SHAH - Folsom CA, US
MURALI RAMADOSS - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 15/00
G06T 15/40
G06T 15/80

Abstract:

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

US Patent:

20210035348, Feb 4, 2021

Filed:

Oct 16, 2020

Appl. No.:

17/072253

Inventors:

- Santa Clara CA, US
Tomas G. AKENINE-MOLLER - Lund, SE
David J. COWPERTHWAITE - Portland OR, US
Kun TIAN - Shanghai, CN
Peter L. DOYLE - El Dorado Hills CA, US
Brent E. INSKO - Portland OR, US
Adam T. LAKE - Portland OR, US

International Classification:

G06T 15/00
G06T 1/20
G06T 1/60
G06T 15/40
G06T 15/50

Abstract:

A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

US Patent:

20200333879, Oct 22, 2020

Filed:

May 5, 2020

Appl. No.:

16/867248

Inventors:

- Santa Clara CA, US
Brent E. INSKO - Portland OR, US
Prasoonkumar SURTI - Folsom CA, US
Adam T. LAKE - Portland OR, US
Peter L. DOYLE - El Dorado Hills CA, US
Daniel POHL - Puchheim, DE

International Classification:

G06F 3/01
G02B 27/00

Abstract:

One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

US Patent:

20200175643, Jun 4, 2020

Filed:

Dec 4, 2018

Appl. No.:

16/208715

Inventors:

- Santa Clara CA, US
ZACK WATERS - PORTLAND OR, US
MICHAEL APODACA - FOLSOM CA, US
JASON SURPRISE - Santa Clara CA, US
PETER DOYLE - GOLD RIVER CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 9/50

Abstract:

Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.

US Patent:

20180082464, Mar 22, 2018

Filed:

Sep 16, 2016

Appl. No.:

15/268495

Inventors:

TOMAS G. AKENINE-MOLLER - Lund, SE
ROBERT M. TOTH - Lund, SE
BRENT E. INSKO - Portland OR, US
PETER L. DOYLE - El Dorado Hills CA, US
PRASOONKUMAR SURTI - Folsom CA, US
MAIYURAN SUBRAMANIAM - Gold River CA, US
CARL JACOB MUNKBERG - Malmo, SE
FRANZ PETRIK CLARBERG - Lund, SE
JON N. HASSELGREN - Bunkeflostrand, SE

International Classification:

G06T 15/00
G06T 17/10
G06T 15/80
G06T 15/30
G06T 15/40
G06T 17/20
G06T 15/04
G06T 15/20

Abstract:

A graphics processing apparatus and method are described. For example, one embodiment of a graphics processing apparatus comprises: an input assembler of a graphics pipeline to determine a first set of triangles to be drawn based on application-provided parameters; a depth buffer to store depth data related to the first set of triangles; a vertex shader to perform position-only vertex shading operations on the first set of triangles in response to an indication that the graphics pipeline is to initially operate in a depth-only mode; a culling and clipping module to read depth values from the depth buffer to identify those triangles in the first set of triangles which are fully occluded by other objects in a current frame and to generate culling data usable to cull occluded triangles, the culling and clipping module to associate the culling data with a replay token to be used to identify a subsequent rendering pass through the graphics pipeline; the input assembler, upon detecting the replay token in the subsequent rendering pass, to access the culling data associated therewith to remove culled triangles from the first set of triangles to generate a second set of triangles; the vertex shader to perform full vertex shading operations on the second set of triangles during the subsequent rendering pass, the replay token to be destroyed during or following the subsequent rendering pass.