Phuc Tong Nguyen

US Patent:

49989120, Mar 12, 1991

Filed:

Mar 2, 1989

Appl. No.:

7/317775

Inventors:

Edward C. Scarbrough - Irving TX
Pietro P. Antich - Richardson TX
Berchmans John - Grand Prairie TX
Phuc D. Nguyen - Dallas TX

Assignee:

Board of Regents, The University of Texas System - Austin TX

International Classification:

A01N 500

US Classification:

600 6

Abstract:

A diverging template (18) for radioactive therapy of cancer within an internal tumor volume by interstitial implants through the skin (78) comprises a proximal surface (34) for positioning adjacent the skin and a distal surface (36) opposite the proximal surface (34). An axis (32) of the template (18) is substantially perpendicular to the proximal surface (34). A plurality of holes (24'-30') are formed in the template (18) from the distal surface (36) to the proximal surface (34) for guiding respective needles (24-30) through the skin (78) and into the tumor volume. The holes comprise at least a first group (28) and a second group (26), each hole of the first group (28) spaced from the axis (32) and forming a first angle therewith that diverges from the distal surface (36) to the proximal surafce (34). Each hole (26) of the second group is spaced from the axis (32) and diverges from the distal surface (36) to the proximal surface (34) at a second angle greater than the first angle. The template of the invention allows the treatment of an internal tumor volume that is greater in lateral area than the area of the proximal surface (34) that includes the groups (26-30) of holes, and avoids problems due to pelvic bone (80) interposition.

US Patent:

20170084682, Mar 23, 2017

Filed:

Dec 7, 2016

Appl. No.:

15/371488

Inventors:

- AUSTIN TX, US
PHUC M. NGUYEN - AUSTIN TX, US
DOUGLAS M. REBER - AUSTIN TX, US

International Classification:

H01L 49/02
H01L 23/482
H01L 23/00
H01L 23/485
H01L 23/31

Abstract:

A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

US Patent:

20160064294, Mar 3, 2016

Filed:

Aug 27, 2014

Appl. No.:

14/470383

Inventors:

DOUGLAS M. REBER - Austin TX, US
Sergio A. Ajuria - Austin TX, US
Phuc M. Nguyen - Austin TX, US

International Classification:

H01L 21/66
H01L 21/48
H01L 23/00

Abstract:

An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

US Patent:

20150200146, Jul 16, 2015

Filed:

Jan 13, 2014

Appl. No.:

14/153417

Inventors:

Douglas M. Reber - Austin TX, US
Sergio A. Ajuria - Austin TX, US
Phuc M. Nguyen - Austin TX, US

International Classification:

H01L 21/66
H01L 23/00
H01L 23/29
H01L 23/10
H01L 21/78

Abstract:

Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

US Patent:

20150061709, Mar 5, 2015

Filed:

Aug 27, 2013

Appl. No.:

14/011160

Inventors:

Sergio A. Ajuria - Austin TX, US
Phuc M. Nguyen - Austin TX, US
Douglas M. Reber - Austin TX, US

International Classification:

G01R 31/28

US Classification:

3247503

Abstract:

A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.

Address:

7903 Peregrine Trl, Arlington, TX 76001

VIN:

1HGCM56347A173834

Make:

HONDA

Model:

ACCORD

Year:

2007