Quan S Tran

US Patent:

7214995, May 8, 2007

Filed:

Sep 30, 2004

Appl. No.:

10/955153

Inventors:

Quan A. Tran - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/82

US Classification:

257415, 257419, 257420, 257618, 257619

Abstract:

According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a top movable electrode, and an actutaion electrode with an undoped polysilicon stopper region to contact the top movable electrode when an actuation current is applied. The undoped polysilicon stopper region prevents actuation charging that accumulates over time in a unipolar actuation condition.

US Patent:

7321275, Jan 22, 2008

Filed:

Jun 23, 2005

Appl. No.:

11/165795

Inventors:

Hanan Bar - Jerusalem, IL
Quan Tran - Fremont CA, US
Joseph Melki - Efrata, IL
John Heck - Berkeley CA, US
Qing Ma - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01P 1/10

US Classification:

333105, 333262

Abstract:

An electromechanical switch includes an actuation electrode, an anchor, a cantilever electrode, a contact, and signal lines. The actuation electrode and anchor are mounted to a substrate. The cantilever electrode is supported by the anchor above the actuation electrode. The contact is mounted to the cantilever electrode. The signal lines are positioned to form a closed circuit with the contact when an actuation voltage is applied between the actuation electrode and the cantilever electrode causing the cantilever electrode to bend towards the actuation electrode in a zipper like movement starting from a distal end of the cantilever electrode.

US Patent:

7510907, Mar 31, 2009

Filed:

Jun 22, 2005

Appl. No.:

11/165465

Inventors:

John Heck - Berkeley CA, US
Qing Ma - San Jose CA, US
Quan Tran - Fremont CA, US
Semeon Altshuler - Rishon-le-Zion, IL
Boaz Weinfeld - Jerusalem, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438106, 438107, 438110, 257E33056

Abstract:

An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.

US Patent:

7602261, Oct 13, 2009

Filed:

Dec 22, 2005

Appl. No.:

11/317960

Inventors:

Quan Tran - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01P 1/10

US Classification:

333105, 333262, 200181

Abstract:

An electromechanical switch includes an actuation electrode, a cantilever electrode, a contact, a suspended conductor, and a signal line. The actuation electrode is mounted to a substrate, the cantilever electrode is suspended proximate to the actuation electrode, and the contact is mounted to the cantilever electrode. The suspended conductor is coupled to the contact and straddles a portion of the cantilever electrode. The signal line is positioned to form a closed circuit with the contact and the suspended conductor when an actuation voltage is applied between the actuation electrode and the cantilever electrode.

US Patent:

7782649, Aug 24, 2010

Filed:

Dec 20, 2007

Appl. No.:

11/961973

Inventors:

Quan Anh Tran - Fremont CA, US
Valluri R. Rao - Saratoga CA, US
Qing Ma - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 11/22

US Classification:

365145, 365 80, 365 87, 369126

Abstract:

Using controlled bias voltage for data retention enhancement in a ferroelectric media is generally described. In one example, an apparatus includes a ferroelectric film including one or more domains, the ferroelectric film having a first surface and a second surface, the first surface being opposite the second surface, an electrode coupled with the first surface, and an electrically conductive thin film coupled with the second surface wherein the electrically conductive thin film is sufficiently conductive that a controlled bias field applied between the electrically conductive thin film and the electrode is sufficient to grow, shrink, or actively maintain the size of the one or more domains disposed between the electrically conductive thin film and the electrode.

US Patent:

8264941, Sep 11, 2012

Filed:

Dec 26, 2007

Appl. No.:

11/964580

Inventors:

Quan Anh Tran - Fremont CA, US
Byong M. Kim - Fremont CA, US
Robert N. Stark - Saratoga CA, US
Nathan R. Franklin - San Mateo CA, US
Qing Ma - San Jose CA, US
Valluri Rao - Saratoga CA, US
Donald E. Adams - Pleasanton CA, US
Li-Peng Wang - San Jose CA, US
Yevgeny V. Anoikin - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11B 9/02

US Classification:

369126, 977947

Abstract:

An arrangement, a method and a system to read information stored in a layer of ferroelectric media. The arrangement includes a layer including a ferroelectric media having one or more ferroelectric domains holding bit charges, a domain corresponding to information; a probe having a tip, wherein the media and the tip are adapted to move relative to one another such that the tip scans the ferroelectric domains of the media while applying a contact force to the domains to generate a direct piezoelectric effect within the domains; and circuitry coupled to the tip and adapted to generate a signal in response to an electrical coupling between the tip and the domains while scanning the tip in contact with the domains, the signal corresponding to a readout signal for ferroelectric bit charges stored in the media.

US Patent:

20090129247, May 21, 2009

Filed:

Nov 12, 2008

Appl. No.:

12/269817

Inventors:

Quan A. Tran - Fremont CA, US
Qing Ma - San Jose CA, US
Donald Edward Adams - Pleasanton CA, US
Nickolai Belov - Los Gatos CA, US
Yevgeny Vasilievich Anoikin - Fremont CA, US

Assignee:

NANOCHIP, INC. - Fremont CA

International Classification:

G11B 9/00

US Classification:

369126, 427131, G9B 9

Abstract:

An information storage device comprises a ferroelectric media, write circuitry to provide a first signal and a second signal to the ferroelectric media, a tip platform and a cantilever operably associated with the tip platform. A tip extends from the cantilever toward the ferroelectric media and includes a first conductive material communicating the first signal from the write circuitry to the ferroelectric media and a second conductive material communicating the second signal from the write circuitry to the ferroelectric media. A insulating material arranged between the first conductive material and the second conductive material to electrically isolate the first conductive material from the second conductive material.

US Patent:

20090168635, Jul 2, 2009

Filed:

Dec 26, 2007

Appl. No.:

11/964608

Inventors:

QUAN ANH TRAN - Fremont CA, US
Nathan R. Franklin - San Mateo CA, US
Qing Ma - San Jose CA, US
Valluri Rao - Saratoga CA, US

International Classification:

G11B 9/00
B05D 5/12

US Classification:

369126, 427127

Abstract:

A memory media and a method to provide same. The memory media includes: a media layer comprising a ferroelectric layer having a bottom surface and a top surface; a plurality of adjacent charge domains defined in the ferroelectric layer, the domains including alternating up domains and down domains each extending between the bottom surface and the top surface; and a trapped charge region adjacent a top surface of the media layer, the trapped charge region including charges in addition to the charges present in the charge domains at regions thereof other than regions adjacent the top surface of the media layer.