Quan V Tran

US Patent:

7510907, Mar 31, 2009

Filed:

Jun 22, 2005

Appl. No.:

11/165465

Inventors:

John Heck - Berkeley CA, US
Qing Ma - San Jose CA, US
Quan Tran - Fremont CA, US
Semeon Altshuler - Rishon-le-Zion, IL
Boaz Weinfeld - Jerusalem, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438106, 438107, 438110, 257E33056

Abstract:

An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.

US Patent:

20100085863, Apr 8, 2010

Filed:

Oct 28, 2008

Appl. No.:

12/260045

Inventors:

Nathan Franklin - San Mateo CA, US
Quan A. Tran - Fremont CA, US
Qing Ma - San Jose CA, US

Assignee:

NANOCHIP, INC. - Fremont CA

International Classification:

G11B 9/00

US Classification:

369126, G9B 9

Abstract:

Provided herein are embodiments for adjusting a built-in bias of a media including a conductive layer and a ferroelectric layer above the conductive layer. In certain embodiments, a voltage signal is applied between the conductive layer of the media and an electrode (provided over at least a portion of the ferroelectric layer) to thereby tune the built-in bias so that the built-in bias moves in a direction of (i.e., towards) the desired built-in bias. In other embodiments, the temperature of the at least a portion of the ferroelectric layer of the media is elevated to thereby tune the built-in bias so that the built-in bias moves in a direction of (i.e., towards) the desired built-in bias. The desired built-in bias can be a zero built-in bias, or a non-zero built-in bias.