Ravi S Shankar

US Patent:

6341300, Jan 22, 2002

Filed:

Jan 29, 1999

Appl. No.:

09/240977

Inventors:

Ravi Shankar - Sunnyvale CA
Subramania I. Sudharsanan - Union City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 738

US Classification:

708605, 708500, 708502

Abstract:

A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.

US Patent:

6349319, Feb 19, 2002

Filed:

Jan 29, 1999

Appl. No.:

09/240765

Inventors:

Ravi Shankar - Sunnyvale CA
Subramania I. Sudharsanan - Union City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 7552

US Classification:

708500, 708502

Abstract:

A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: in each interval i. The reciprocal square root computation uses the piece-wise quadratic approximation in the form: in each interval i. The coefficients {overscore (A)} , {overscore (B)} , and {overscore (C)} , and A , B , and C are derived for the square root operation and for the reciprocal square root operation to reduce the least mean square error using a least squares approximation of a plurality of equally-spaced points within an interval. In one embodiment, 256 equally-spaced intervals are defined to represent the 23 bits of the mantissa. The coefficients are stored in a storage and accessed during execution of the square root or reciprocal square root computation instruction.

US Patent:

6351760, Feb 26, 2002

Filed:

Jan 29, 1999

Appl. No.:

09/240312

Inventors:

Ravi Shankar - Sunnyvale CA
Subramania I. Sudharsanan - Union City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 752

US Classification:

708654, 708504

Abstract:

A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of âleast mean square errorâtechniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x , Ax , and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.

US Patent:

6678710, Jan 13, 2004

Filed:

Nov 3, 2000

Appl. No.:

09/706467

Inventors:

Ravi Shankar - Santa Clara CA
Subramania I. Sudharsanan - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 700

US Classification:

708517

Abstract:

A computation unit employs a logarithmic number system that uses a logarithmic numerical representation that differs from an IEEE standard representation to improve the efficiency of computation, both by reducing the time expended in performing the computation and by reducing the size of the integrated circuit that performs the computation. The illustrative computation unit employs a numerical representation that is similar to the IEEE format except that the sign term is omitted. Thus only positive numbers are represented. The value of the mantissa is defined as a fractional number between zero and one. The logarithmic number system is a useful number system domain for multiplication, division, reciprocal, square root, and power computations using multiplication, division, and square root computation techniques described by following equations:.

US Patent:

7257611, Aug 14, 2007

Filed:

May 2, 2000

Appl. No.:

09/562785

Inventors:

Ravi Shankar - San Jose CA, US
David S. Labuda - Half Moon Bay CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 15/16

US Classification:

709201, 709209, 709211, 709217, 709229, 709234, 455 201, 455 302, 455405, 705 30, 705 32, 713323

Abstract:

Methods and architectures for implementing a fault tolerant real time event processing system are provided. The system includes at least one satellite and at least one primary data center. The system remains operational when the primary data center is unavailable to the satellite. The system includes business logic that is divided into logic that can be run effectively at a satellite, and logic that can be run at the main data center to result in effective decisions. When the network connection is impaired or the main data center is unavailable, the satellite can process an incoming event locally. The system includes procedures so that events processed at a satellite during a period of noncommunication with the primary data center will be entered into the primary data center records at a later point.

US Patent:

7406471, Jul 29, 2008

Filed:

Sep 27, 2001

Appl. No.:

09/967493

Inventors:

Ravi Shankar - Cupertino CA, US
Keith M. Brefczynski - Cupertino CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 17/30
G06F 7/00

US Classification:

707 10, 707 4, 7071041

Abstract:

Methods and architectures for implementing a scalable multi-database event processing system are provided. In one embodiment, selected account data is aggregated for all subscribers (aggregated subscriber-specific data) and a copy included on each database. In one embodiment, selected data that is not subscriber specific and that may apply to many accounts (“global data”) is also maintained and copied to each database. The global data preferably includes business data that is frequently required during operation of the system, such as pricing data. A transaction that requires business data and access to an account is processed using the copy of the business data that is on the database on which the account is located. In an embodiment, the aggregated subscriber-specific data is used in performing searches.

US Patent:

7669179, Feb 23, 2010

Filed:

Nov 4, 2003

Appl. No.:

10/700431

Inventors:

Sanjeev Gupta - San Jose CA, US
Ravi Shankar - Sunnyvale CA, US
Ajai Kapoor - Cupertino CA, US
Prakash Kumar Pati - San Jose CA, US
Corvin Bazgan - San Carlos CA, US
Subbarao Nimmakayala - Livermore CA, US

Assignee:

Realization Technologies, Inc. - San Jose CA

International Classification:

G06F 9/44

US Classification:

717101

Abstract:

A method on a computer for providing critical chain-based project management across a plurality of projects is disclosed. The method includes generating a plurality of plans, each of the plurality of plans corresponding to one of the plurality of projects, wherein a project comprises at least one task. The method further includes generating buffers for each of the plurality of projects and reconciling project resources among the plurality of projects. The method further includes executing the plurality of project plans, including allowing a user to manage the buffers across the plurality of projects. The user is further provided with information associated with buffers for the plurality of projects, so as to evaluate the status of the plurality of projects. Additionally, the user is provided with task prioritization for any task of the plurality of projects, wherein task prioritization is calculated across the plurality of projects.

US Patent:

7774742, Aug 10, 2010

Filed:

Jun 8, 2005

Appl. No.:

11/147479

Inventors:

Sanjeev Gupta - San Jose CA, US
Ajai Kapoor - San Jose CA, US
Ravi Shankar - San Jose CA, US
Prakash Pati - San Jose CA, US
Subramanian Muthu - Santa Clara CA, US
Anthony Hoang - Milpitas CA, US
Sridharan Chandrasekaran - San Jose CA, US

Assignee:

Realization Technologies, Inc. - San Jose CA

International Classification:

G06F 9/44

US Classification:

717101, 717102, 717103, 717100

Abstract:

A method on a computer for providing critical chain-based project management is disclosed. The method includes receiving at least one project plan for a project comprising a plurality of tasks and calculating a task priority for each of the plurality of tasks based on the at least one project plan. The method further includes receiving at least one sub-task for a first task of the plurality of tasks and assigning the at least one sub-task a task priority identical to the task priority of the first task. In one alternative, the method further includes receiving a new task priority for the first task, assigning the new task priority to the first task and assigning the new task priority to the at least one sub-task of the first task. The method may also include an interface to allow starting of sub-tasks only when the parent task is started.