Richard T Duncan

US Patent:

6437958, Aug 20, 2002

Filed:

Jan 21, 2000

Appl. No.:

09/489540

Inventors:

Richard L. Duncan - Bedford TX
Joseph D. Wert - Arlington TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H02H 900

US Classification:

361 911, 361 56, 361111

Abstract:

An output driver prevents gate oxide breakdown and reverse charge leakage from a bus to the internal power supply. When the voltage on the bus exceeds the internal supply voltage or when the driver is powered down, a reference voltage generator provides intermediate voltages to prevent the development of excessive gate-source, gate-drain, and gate-backgate voltages in the driver. An upper protection circuit and a lower protection circuit multiplex the intermediate voltages to ensure driver protection and proper operation. A buffering circuit turns off a buffering transistor to block charge leakage to the internal power supply when the bus voltage is greater than the internal power supply voltage. A logic protection circuit prevents the bus voltage from appearing at the control terminal of the driver.

US Patent:

6987404, Jan 17, 2006

Filed:

Oct 10, 2003

Appl. No.:

10/684093

Inventors:

Richard L. Duncan - Bedford TX, US

Assignee:

VIA Technologies, Inc. - Fremont CA

International Classification:

H03K 5/135

US Classification:

327141, 327144, 375356

Abstract:

An improved signal synchronizing circuit for prohibiting signals traveling from a first clock domain operating with a first clock to a second clock domain operating with a second clock when the first clock is not active. The synchronizing circuit comprising at least one signal receiving module for receiving at least one selected signal in the first clock domain, a detection circuit producing a detection signal indicating that the first clock is active, and at least one output selection module for passing the selected signal from the first clock domain to the second clock domain when the first clock is active.

US Patent:

7000131, Feb 14, 2006

Filed:

Nov 14, 2003

Appl. No.:

10/713838

Inventors:

William V. Miller - Arlington TX, US
Richard L. Duncan - Bedford TX, US

Assignee:

Via Technologies, Inc. - Taipei

International Classification:

G06F 1/32
G06F 13/00

US Classification:

713322, 713323, 713324, 713601, 710107, 710113

Abstract:

The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.

US Patent:

7290153, Oct 30, 2007

Filed:

Nov 8, 2004

Appl. No.:

10/983913

Inventors:

Richard Duncan - Bedford TX, US

Assignee:

VIA Technologies, Inc. - Hsin-Tien, Taipei

International Classification:

G06F 1/32

US Classification:

713320, 713322, 713323, 712209, 712210

Abstract:

Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a present instruction, and at least one subset instruction decoder configured to determine whether the present instruction potentially needs a register. A memory element is also included and is configured to hold data from a previous instruction. A selector is included and configured to output either the previous instruction or the decoded present instruction, based on the subset instruction decoder.

US Patent:

7555609, Jun 30, 2009

Filed:

Oct 27, 2006

Appl. No.:

11/553586

Inventors:

Richard Duncan - Bedford TX, US
William V. Miller - Arlington TX, US
Daniel Davis - Arlington TX, US

Assignee:

VIA Technologies, Inc. - Hsin-Tien, Taipei

International Classification:

G06F 12/00

US Classification:

711137, 711155, 711213

Abstract:

Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus masters similarly coupled to the system bus. The memory controller is configured to receive requests to read or write data from memory from bus masters of the computer system. If the memory controller receives an initial request from certain bus masters, the memory controller is further configured to anticipate a future request from certain bus masters and prefetch data on behalf of certain bus masters for rapid delivery following a subsequent request to read data from memory submitted by the certain bus masters.

US Patent:

8437169, May 7, 2013

Filed:

Dec 20, 2010

Appl. No.:

12/973362

Inventors:

Degang Xia - Allen TX, US
Steven Chacko - League City TX, US
Richard Lawrence Duncan - Bedford TX, US
Chuan Ni - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 11/22

US Classification:

365145, 365229, 365228

Abstract:

A circuit to protect data on an FRAM during a read operation includes an FRAM voltage regulator having an output to supply an FRAM operating voltage to the FRAM. A voltage monitor monitors a supply voltage for the FRAM to generate a voltage fault signal if the supply voltage falls below a predetermined value. And a circuit responsive to the voltage fault signal maintains the FRAM operating voltage above a voltage required to assure data integrity of the FRAM for a sufficient time required to perform an FRAM read operation.

US Patent:

7263621, Aug 28, 2007

Filed:

Nov 15, 2004

Appl. No.:

10/989090

Inventors:

Richard Duncan - Bedford TX, US

Assignee:

VIA Technologies, Inc. - Taipei

International Classification:

G06F 1/32

US Classification:

713320, 712209, 712210

Abstract:

The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit instruction decoder for decoding instructions with 32-bit words, a word length select for indicating a present instruction's word length, and a first selector for routing the instruction into the 16-bit decoder when the present instruction is 16-bits long. The first selector is also configured to route a previous instruction into the 16-bit decoder, maintaining the 16-bit decoder's present state. A second selector is configured to route the instruction into the 32-bit decoder when the present instruction is 32-bits long. The second selector is also configured to route a past instruction into the 32-bit decoder to maintain the 32-bit decoder's present state.

US Patent:

20040230781, Nov 18, 2004

Filed:

May 16, 2003

Appl. No.:

10/439941

Inventors:

Charles Shelor - Arlington TX, US
Richard Duncan - Bedford TX, US

Assignee:

VIA-Cyrix, Inc. - Fremont CA

International Classification:

G06F009/00

US Classification:

712/239000

Abstract:

A method and system is disclosed for predicting whether a conditional instruction is to be executed in a processor. The processor processes instructions through processing stages including at least a decode stage, an execute stage, and one or more intermediate processing stages therebetween. First, a current condition status of the processor is detected, wherein the condition status shows whether one or more conditions for executing the conditional instruction have been satisfied. After detecting whether one or more associated instructions as being processed during the intermediate processing stages have impacted or will impact the conditions to be satisfied, it is determined whether the conditional instruction should be terminated at the decode stage based on the detected current condition status and the detected impact on the conditions due to the processing of the associated instructions. If it is predicted that there are unsatisfied conditions for executing the conditional instruction in the execute stage, the conditional instruction is terminated in the decode stage so as to avoid utilizing additional processor resources.