Robert E Fuller

US Patent:

6350640, Feb 26, 2002

Filed:

Jul 18, 1994

Appl. No.:

08/276290

Inventors:

Robert T. Fuller - Melbourne Beach FL
Chris McCarty - Melbourne FL
John T. Gasner - Satellite Beach FL
Michael D. Church - Sebastian FL

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L 218238

US Classification:

438202, 438234

Abstract:

To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.

US Patent:

58083537, Sep 15, 1998

Filed:

Jun 20, 1996

Appl. No.:

8/666258

Inventors:

Robert T. Fuller - Melbourne Beach FL
Howard L. Evans - Palm Bay FL
Michael J. Morrison - Malabar FL
David A. DeCrosta - Melbourne FL
Robert K. Lowry - Melbourne Beach FL

Assignee:

Harris Corporation - Melbourne FL

International Classification:

H01L 29792

US Classification:

257651

Abstract:

A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112. 2 of the same layer as the polysilicon gate 112. 1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103. 2. A positive voltage applied to N well 103. 2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112. 2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

US Patent:

58048464, Sep 8, 1998

Filed:

May 28, 1996

Appl. No.:

8/654393

Inventors:

Robert T. Fuller - Melbourne Beach FL

Assignee:

Harris Corporation - Melbourne FL

International Classification:

H01L 2982

US Classification:

257252

Abstract:

The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a gate that is provided on both sides with an insulating spacer to electrically isolate it from the source and drain. The planarized tungsten layer comprises a first portion whose lower surface is in contact with a polysilicon layer of the gate. The lower surface of each of the second and third portions of the tungsten layer is in contact with the source and drain, respectively. The second and third portions are insulated from the first portion by the insulating spacers, and the upper surfaces of all the portions comprise a coplanar surface. Planarization of the deposited metal layer thus provides ohmic contact at substantially the same level to the source, drain, and gate. In a self-aligned raised source/drain MOS device formed by the process of the invention, the second and third portions of the planarized metal layer preferably extend laterally over the field oxide and are characterized by an upper:lower surface width ratio of from about 2:1 to 4:1.

US Patent:

56704135, Sep 23, 1997

Filed:

Jan 16, 1996

Appl. No.:

8/586556

Inventors:

Robert T. Fuller - Melbourne Beach FL

Assignee:

Harris Corporation - Palm Bay FL

International Classification:

H01L 2176

US Classification:

437 69

Abstract:

A radiation hardening isolation technique uses a poly buffered LOCOS structure (34, 36) to protect the device areas during field oxide 40 formation. The field oxide 40 is removed, and the polysilicon structure 34 is covered with a PSG or BPSG layer 42. Layer 42 is planarized and the polysilicon 34 is removed to provide a self-aligned device region 31.

US Patent:

61301728, Oct 10, 2000

Filed:

Apr 16, 1998

Appl. No.:

9/061602

Inventors:

Robert T. Fuller - Melbourne Beach FL
Howard L. Evans - Palm Bay FL
Michael J. Morrison - Malabar FL
David A. DeCrosta - Melbourne FL
Robert K. Lowry - Melbourne Beach FL

Assignee:

Intersil Corporation - Palm Bay FL

International Classification:

H01L 2131

US Classification:

438783

Abstract:

A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112. 2 of the same layer as the polysilicon gate 112. 1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103. 2. A positive voltage applied to N well 103. 2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112. 2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.