Robert H Pearson

US Patent:

54695422, Nov 21, 1995

Filed:

Jul 22, 1991

Appl. No.:

7/733767

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert B. Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1100

US Classification:

39520001

Abstract:

Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.

US Patent:

62020978, Mar 13, 2001

Filed:

Jan 17, 1995

Appl. No.:

8/373052

Inventors:

David James Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert Bernard Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15173

US Classification:

709238

Abstract:

Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.

US Patent:

53275705, Jul 5, 1994

Filed:

Jul 22, 1991

Appl. No.:

7/734432

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert B. Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

395800

Abstract:

A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.

US Patent:

52766845, Jan 4, 1994

Filed:

Jul 22, 1991

Appl. No.:

7/734359

Inventors:

Robert B. Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 324

US Classification:

370 941

Abstract:

An I/O Processor (28) includes a two channel receiver (28b) and a two channel transmitter (28c) coupled to a high speed communications channel. For the receiver a status memory, specifically a FIFO (44a, 44b), stores structuring information that indicates the beginnings (SOP) and endings (EOP) of PACKETS, as well as, for each BURST of data words within a packet, an indication of the occurrence of the BURST and a length (L) of the BURST. Additionally, there is an indication for each BURST of the presence of any errors occurring during the BURST. A corresponding data FIFO (40a, 40b) contains only the received data words, without any structuring information. A device reads both of the FIFOS, subsequent to the reception of one or more PACKETS, so as to reconstruct the original format of the received data. For the transmitter a structure control FIFO (46a, 46b) stores the structuring information for an associated data FIFO (40c, 40d) , the transmitted data being structured in accordance with the structuring information. The receiver and the transmitter each include a high speed internal data path (42a, 42b) and a lower speed data path (54a, 54b) which are coupled together during slave read and write cycles, and which are decoupled during high speed DMA cycles.

US Patent:

20180059118, Mar 1, 2018

Filed:

Sep 22, 2017

Appl. No.:

15/712972

Inventors:

- Franklin Lakes NJ, US
Christian Sandmann - Wayne NJ, US
William Shannon Dillmore - Raleigh NC, US
James L. Schram - Knightdale NC, US
W. William Stewart - Cary NC, US
Robert E. Pearson - Durham NC, US
Helen Hsieh - Durham NC, US
Steven Keith - Chapel Hill NC, US
Rajendra R. Bhat - Raleigh NC, US
Andrea Liebmann-Vinson - Wake Forest NC, US
Adam Craig Curry - Raleigh NC, US
Alexander G. Lastovich - Raleigh NC, US

Assignee:

BECTON DICKINSON AND COMPANY - Franklin Lakes NJ

International Classification:

G01N 33/58
G01N 21/65
G01N 33/543

Abstract:

Disclosed herein are diagnostic assays using surface enhanced Raman spectroscopy (SERS)-active particles, including liquid-based assays; magnetic capture assays; microparticle-nanoparticle satellite structures for signal amplification in an assay; composite SERS-active particles useful for enhanced detection of targets; and sample tubes and processes for using the same.