Robert Howard Perlman

US Patent:

50536311, Oct 1, 1991

Filed:

Apr 2, 1990

Appl. No.:

7/503817

Inventors:

Robert M. Perlman - San Jose CA
Prem Sobel - Sunnyvale CA
Brian D. McMinn - Austin TX
Robert C. Thaden - Austin TX
Glenn A. Tamura - Austin TX
Thomas W. Lynch - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

364748

Abstract:

A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.

US Patent:

50580485, Oct 15, 1991

Filed:

Apr 2, 1990

Appl. No.:

7/503819

Inventors:

Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

364748

Abstract:

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

US Patent:

53275713, Jul 5, 1994

Filed:

Aug 10, 1993

Appl. No.:

8/104398

Inventors:

Brian D. McMinn - Austin TX
Robert H. Perlman - San Jose CA
Prem Sobel - Pondicherry, IN

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9315
G06F 9312
G06F 930

US Classification:

395800

Abstract:

A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

US Patent:

52671860, Nov 30, 1993

Filed:

Jul 23, 1991

Appl. No.:

7/734762

Inventors:

Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

364748

Abstract:

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.